Development and Evaluation of a Robust Sandwich Immunoassay System Detecting Serum WFA-Reactive IgA1 for Diagnosis of IgA Nephropathy

Aberrant glycosylation of IgA1 is involved in the development of IgA nephropathy (IgAN). There are many reports of IgAN markers focusing on the glycoform of IgA1. None have been clinically applied as a routine test. In this study, we established an automated sandwich immunoassay system for detecting aberrant glycosylated IgA1, using Wisteria floribunda agglutinin (WFA) and anti-IgA1 monoclonal antibody. The diagnostic performance as an IgAN marker was evaluated. The usefulness of WFA for immunoassays was investigated by lectin microarray. A reliable standard for quantitative immunoassay measurements was designed by modifying a purified IgA1 substrate. A validation study using multiple serum specimens was performed using the established WFA-antibody sandwich automated immunoassay. Lectin microarray results showed that WFA specifically recognized N-glycans of agglutinated IgA1 in IgAN patients. The constructed IgA1 standard exhibited a wide dynamic range and high reactivity. In the validation study, serum WFA-reactive IgA1 (WFA+-IgA1) differed significantly between healthy control subjects and IgAN patients. The findings indicate that WFA is a suitable lectin that specifically targets abnormal agglutinated IgA1 in serum. We also describe an automated immunoassay system for detecting WFA+-IgA1, focusing on N-glycans.     

P-MOSFET's with ultra-shallow solid-phase-diffused drain structureproduced by diffusion from BSG gate-sidewall

A p-MOSFET structure with solid-phase diffused drain (SPDD) is proposed for future 0.1-μm and sub-0.1-μm devices. Highly doped ultrashallow p⁺ source and drain junctions have been obtained by solid-phase diffusion from a highly doped borosilicate glass (BSG) sidewall. The resulting shallow, high-concentration drain profile significantly improves short channel effects without increasing parasitic resistance. At the same time, an in situ highly-boron-doped LPCVD polysilicon gate is introduced to prevent the transconductance degradation which arises in ultrasmall p-MOSFETs with lower process temperature as a result of depletion formation in the p⁺-polysilicon gate. Excellent electrical characteristics and good hot-carrier reliability are achieved     

A Si bipolar 1.4-GHz time space switch LSI for B-ISDN

A 155-MB/s 32×32 Si bipolar switch LSI designed for wide application in the broadband ISDN was implemented. The operating speed is 1.4 GHz using an A-BSA Si bipolar process. Its throughput is 5.0 Gb/s by handling four 1.4-GHz interfaces, each of which supports an eight-channel multiplexed data stream. To realize a highly integrated high-speed bipolar LSI, power consumption and chip area should be reduced. Two technologies were developed for the LSI: (1) an active pull-down circuit with an embedded bias circuit in each gate, and (2) a modified standard cell with overlapped cell-channel structure. Using these technologies, total power consumption and chip area were reduced to 60% and 70%, respectively, of what is expected when conventional emitter-coupled logic (ECL) technologies and standard cell structures are used. The LSI evaluation results show that the developed LSI has sufficient performance to realize a large-scale B-ISDN switching system     

Ultrastructural and cytochemical study of the odontoclasts in physiologic root resorption of human deciduous teeth.

Using extracted human deciduous teeth undergoing physiologic root resorption, this author studied the ultrastructural and cytochemical features of odontoclasts. The scanning electron microscopic observation of trypsin-treated dentin and cementum surfaces of resorption lacunae showed the exposure of collagen fibrils and prominent loss of the peritubular matrices around the dentinal tubules. In the resorption lacunae formed in enamel, there was dissolution of either the rod or the interrod regions. The odontoclasts developed extensive ruffled borders apposed to these resorbing matrices and had round phagosomes containing tannic acid-stainable fine amorphous inclusions, which were identical to those in the extracellular canals of the ruffled borders. The odontoclasts did not phagocytose the collagen fibrils. The odontoclasts showed the enzymatic activities of the acid trimetaphosphatase and acid p-nitrophenyl phosphatase (p-NPPase) in the Golgi-lysosome system, the ruffled border region, and along the resorbing dentin surfaces. The p-NPPase activity was inhibited by sodium tartrate. Also, the odontoclasts showed H(+)-K(+)-ATPase activity in the cytoplasm along the plasma membranes including those of ruffled border and the limiting membranes of the lysosomes. These results suggest that: 1) the odontoclasts are associated with resorption of non-collagenous organic matrices and/or extracellularly-degraded collagenous fragments rather than the incorporation of intact collagen fibrils; 2) the odontoclasts release the hydrolytic enzymes onto the lacunal surfaces and/or the lysosomes for the extra/intracellular degradation of the organic matrices; and 3) they also have H(+)-K(+)-ATPase for extracellular demineralization of the inorganic crystals.     

Dependence of the frequency shift of the optical-microwave doubleresonance signal in the Cs D2 line on the pumpingfrequency and power of a GaAs semiconductor laser

The OMDR (optical-microwave double resonance) effect in the Cs D₂ line was studied for realizing a gas-cell-type Cs atomic frequency standard. A glass cell containing Cs with buffer gases (Ar/N₂=1.26, total pressure=39 torr) was placed in a TE₀₁₂ mode microwave cavity at a temperature of 45°C and was pumped using a GaAs semiconductor laser frequency locked to an external interferometer tuned to the 6P_3/2 (F=2,3,4)←6 S_1/2(F=3) transition. The OMDR signal appearing at the resonance to the F=4←3 hyperfine transition of the 6S_1/2 state shifted with detuning of the laser frequency and with change of the laser and microwave powers. The dependence of the shift on these variables around an optimum operating condition was obtained as, Δν_MW[Hz]=-(0.31±0.02) {1+(0.44±0.15) (ΔP_L/P_L)} Δν_L [MHz]-10(ΔV_MW/V _MW)     

0.5-μm 3.3-V BiCMOS standard cells with 32-kilobyte cache andten-port register file

BiCMOS standard cell macros, including a 0.5-W 3-ns register file, a 0.6-W 5-ns 32-kbyte cache, a 0.2-W 3-ns table look-aside buffer (TLB), and a 0.1-W 3-ns adder, are designed with a 0.5-μm BiCMOS technology. A supply voltage of 3.3 V is used to achieve low power consumption. Several BiCMOS/CMOS circuits, such as a self-aligned threshold inverter (SATI) sense amplifier and an ECL HIT logic are used to realize high-speed operation at the low supply voltage. The performance of the BiCMOS macros is verified using a fabricated test chip     

Sub-50-nm physical gate length CMOS technology and beyond usingsteep halo

Sub-50-nm CMOS devices are investigated using steep halo and shallow source/drain extensions. By using a high-ramp-rate spike annealing (HRR-SA) process and high-dose halo, 45-nm CMOS devices are fabricated with drive currents of 650 and 300 μA/μm for an off current of less than 10 nA/μm at 1.2 V with T_ox^inv =2.5 nm. For an off current less than 300 nA/μm, 33-nm pMOSFETs have a high drive current of 400 uA/μm. Short-channel effect and reverse short-channel effect are suppressed simultaneously by using the HRR-SA process to activate a source/drain extension (SDE) after forming a deep source/drain (S/D). This process sequence is defined as a reverse-order S/D (R-S/D) formation. By using this formation, 24-nm nMOSFETs are achieved with a high drive current of 800 μA/μm for an off current of less than 300 μA/μm at 1.2 V. This high drive current might be a result of a steep halo structure reducing the spreading resistance of source/drain extensions     

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance operation. Nitrogen concentration in gate oxynitride was optimized to reduce gate current I/sub g/ and to prevent boron penetration in the pFET. The thermal budget in the middle of the line (MOL) process was reduced enough to realize shallower junction depth in the S/D extension regions and to suppress gate poly-Si depletion. Finally, the current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/=0.85 V (at I/sub off/=100 nA//spl mu/m) were achieved and they are the best values for 35 nm gate length CMOS reported to date.     

Erase/write cycle tests of n-MOSFETs with Si-implantedgate-SiO2

To discuss the applicability of a MOSFET with Si-implanted gate-SiO₂ of 50 nm thickness to a non volatile random access memory (NVRAM) operating more than 3.3×10¹⁵ erase/write (E/W) cycles, E/W-cycle tests were performed up to 10¹¹ cycles by measuring the hysteresis curve observed in a source follower MOSFET in which a sine-wave voltage of 100 kHz was supplied to the gate. Degradations in the threshold-voltage window of 15 V and gain factor were scarcely observed in a MOSFET with Si-implantation at 50 keV/1×10¹⁶ cm^-2 at a gate voltage of ±40 V. Those degradations observed in a MOSFET with 25 keV/3×10¹⁶ cm^-2 were improved by lowering the gate voltage from ±40 V to ±30 V in sacrificing the smaller threshold-voltage window from 20 to 8.5 V     

A real-time motion estimation and compensation LSI with wide searchrange for MPEG2 video encoding

This paper presents a motion estimation and compensation large scale integration (LSI) for the MPEG2 standard. An embedded RISC processor and special hardware modules enable the LSI to achieve a sufficient ability to perform real-time operation and provide the availability to realize many kinds of block matching algorithms. Using a three-step hierarchical telescopic search algorithm, a single chip accomplishes real-time motion estimation with search ranges of ±32.5×±32.5 pixels for motion vectors. The chip was fabricated using 0.5-μm CMOS technology and has an area of 16.5×16.5 mm² and 2.0 M transistors