Lossless,Passive Transportation of Low Surface Tension Liquids Induced by Patterned Omniphobic Liquidlike Polymer Brushes

Surfaces enabling directional liquid transportation are of great interest for a wide range of applications such as water collection, microfluidics, and heat transfer systems. Surfaces capable of lossless, long-range passive transportation of low surface tension (LST) liquids using wettability patterned, liquidlike coatings with minimal contact angle hysteresis are reported. Lossless LST droplet travel distances over 150 mm are achieved, enabled by a two-phase transportation mechanism: morphological transformation from a bulge to a channel shape, followed by directional transportation along the asymmetrical wedge-shaped channel. The developed surfaces can split, merge, and precisely transport various low-surface tension liquids, including alcohols, alkanes, and solvents. The developed transportation strategy can also enhance LST liquid dropwise condensation through continuous removal of the condensate, even on horizontally positioned surfaces without the assistance of gravity.     

Images of a First‐Order Spin‐Reorientation Phase Transition in a Metallic Kagome Ferromagnet

First‐order phase transitions, where one phase replaces another by virtue of a simple crossing of free energies, are best known between solids, liquids, and vapors, but they also occur in a wide range of other contexts, including even elemental magnets. The key challenges are to establish whether a phase transition is indeed first order, and then to determine how the new phase emerges because this will determine thermodynamic and electronic properties. Here it is shown that both challenges are met for the spin reorientation transition in the topological metallic ferromagnet Fe₃Sn₂. The magnetometry and variable temperature magnetic force microscopy experiments reveal that, analogous to the liquid–gas transition in the temperature–pressure plane, this transition is centered on a first‐order line terminating in a critical end point in the field‐temperature plane. The nucleation and growth associated with the transition is directly imaged, indicating that the new phase emerges at the most convoluted magnetic domain walls for the high temperature phase and then moves to self‐organize at the domain centers of the high temperature phase. The dense domain patterns and phase coexistence imply a complex inhomogenous electronic structure, which can yield anomalous contributions to the electrical conductivity.     

Open‐Shell Donor–Acceptor Conjugated Polymers with High Electrical Conductivity

Conductive polymers largely derive their electronic functionality from chemical doping, processes by which redox and charge‐transfer reactions form mobile carriers. While decades of research have demonstrated fundamentally new technologies that merge the unique functionality of these materials with the chemical versatility of macromolecules, doping and the resultant material properties are not ideal for many applications. Here, it is demonstrated that open‐shell conjugated polymers comprised of alternating cyclopentadithiophene and thiadiazoloquinoxaline units can achieve high electrical conductivities in their native “undoped” form. Spectroscopic, electrochemical, electron paramagnetic resonance, and magnetic susceptibility measurements demonstrate that this donor–acceptor architecture promotes very narrow bandgaps, strong electronic correlations, high‐spin ground states, and long‐range π‐delocalization. A comparative study of structural variants and processing methodologies demonstrates that the conductivity can be tuned up to 8.18 S cm^?1. This exceeds other neutral narrow bandgap conjugated polymers, many doped polymers, radical conductors, and is comparable to commercial grades of poly(styrene‐sulfonate)‐doped poly(3,4‐ethylenedioxythiophene). X‐ray and morphological studies trace the high conductivity to rigid backbone conformations emanating from strong π‐interactions and long‐range ordered structures formed through self‐organization that lead to a network of delocalized open‐shell sites in electronic communication. The results offer a new platform for the transport of charge in molecular systems.     

为烟雾检测器提供遥测报警

基于离子的烟雾检测器便宜且有效,除了安装在室内外,还经常安装在车库及其他室外建筑中,这些设计需要把报警信号送回房间或家庭安全系统.图1所示电路通过检测传感器警报时的工作电流提供检测器的遥测输出.正常监视模式下,工作电流只有50μA,触发报警时电流超过3mA.该电路由烟雾检测器的内部电池供电,对检测器影响很小.图中所示比较器具有较宽的工作电压范围、低工作电流和内置电压基准.典型静态工作电流小于3μA.     

平台2015:Intel处理器及平台在下一个十年的演化

毫无疑问,近年来计算技术取得了长足的进步。但是,在未来的十年,主流计算技术中新的工作量、使用模式的出现及变化对未来的计算平台提出的要求,与过去十年所取得的进展也差不多,这些巨大的要求包括:更高的性能、更低的功率密度、更好的功能可扩展性。倘若出现这些使用计算机的震撼性的变化,我们怎样定义和构架未来的计算平台,就将不得不做出引人注目的改变。要整体地理解和满足的,不仅仅有计算的需要,而且还有接口以及系统基础设施的需要。Intel对这三个基础平台要素的演化的长期设想,以及驱动演化的架构的创新和核心能力,即是我们称之为平台2015(Platform2015)的内容。除了考察相关的趋势、使用、平台处理含意之外,本文将集中在平台2015的计算单元,描述Intel微处理器架构在未来十年的演化。     

Analysis of external latch-up protection test structure design using numerical simulation

With each new CMOS technology the latch-up sensitivity and effects of prevention strategies change. Products built in these technologies must adhere to stringent guidelines for latch-up ‘Hardness’, and for this reason characterisation of new technologies is needed through the use of test structures. This paper shows a numerical simulation approach which can determine the relative effectiveness of guard-rings in ESD protection device test structures. In this work, time taken to characterise latch-up protection test structures and to chose a protection strategy is greatly reduced by using numerical simulations to design the test structures. The results presented are for variations to the guard-rings for two technologies. Included in these are the typical simulation times and resources required. The technique outlined has the joint advantages of providing accurately representative simulations of the technology and test structure layout in a practical time frame.     

Integrated Saltwater Desalination and Energy Storage through a pH Neutral Aqueous Organic Redox Flow Battery

Here, a pH neutral aqueous organic redox flow battery (AORFB) consisting of three electrolytes channels (i.e., an anolyte channel, a catholyte channel, and a central salt water channel) to achieve integrated energy storage and desalination is reported. Employing a low cost, chemically stable methyl viologen (MV) anolyte, and sodium ferrocyanide catholyte, this desalination AORFB is capable of desalinating simulated seawater (0.56 m NaCl) down to 0.023 m salt concentration at an energy cost of 2.4 W h L^?1 of fresh water—competitive with current reverse osmosis technologies. Simultaneously, the cell delivers stored energy at 79.7% efficiency with a cell voltage of 0.85 V. Furthermore, the cell is also capable of higher current operation up to 15 mA cm^?2, providing 4.55 mL of fresh water per hour. Combining energy storage and water desalination into such a bifunctional device offers the opportunity to address two growing global issues from one hardware installation.     

A 16-Bit by 16-Bit MAC Design Using Fast 5:3 Compressor Cells

3:2 counters and 4:2 compressors have been widely used for multiplier implementations. In this paper, a fast 5:3 compressor is derived for high-speed multiplier implementations. The fast 5:3 compression is obtained by applying two rows of fast 2-bit adder cells to five rows in a partial product matrix. As a design example, a 16-bit by 16-bit MAC (Multiply and Accumulate) design is investigated both in a purely logical gate implementation and in a highly customized design. For the partial product reduction, the use of the new 5:3 compression leads to 14.3% speed improvement in terms of XOR gate delay. In a dynamic CMOS circuit implementation using 0.225 m bulk CMOS technology, 11.7% speed improvement is observed with 8.1% less power consumption for the reduction tree.     

The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections

The effect of interconnect coupling capacitances on neighboring CMOS logic gates driving coupled interconnections strongly depends upon signal activity. A transient analysis of two capacitively coupled CMOS logic gates is presented in this paper for different combinations of signal activity. The uncertainty of the effective load capacitance and propagation delay due to signal activity is addressed. Analytical expressions characterizing the output voltage and propagation delay are also presented for different signal activity conditions. The propagation delay based on these analytical expressions is within 3% as compared to SPICE, while the estimated delay neglecting the difference between the load capacitances can exceed 45%. The logic gates should be properly sized to balance the load capacitances in order to minimize any uncertainty in the delay and load. The peak noise voltage on a quiet interconnection determined from the analytical expressions is within 4% of SPICE. The peak noise voltage on a quiet interconnection can be minimized if the effective output conductance of the quiet logic gate driving the interconnect is increased.     

超越“纳米级”设计时代

毫无疑问,我们正在跨入“纳米级”设计时代（处于1000nm到1nm级别的设计）的后期阶段。在未来18个月内,我们将开始部署32nm设计流程;而且,从32nm跨越到22nm所存在的障碍已经被攻克。我们将会在65nm和45/40nm之间采用有效率的、以价值为基础的设计流程。我们将乐于获得多CPU芯片和虚拟软件支持带来的优越性,凭借着新型设计平台的威力,迎来产品和应用新一轮的蓬勃发展。新型设计平台使设计公司可以充分发挥各种成本／功能／价值工艺节点之所长,满足当前市场上的定制需求。