An Area Optimization Method for Digital Filter Design

In this paper, we propose an efficient design method for area optimization in a digital filter. The conventional methods to reduce the number of adders in a filter have the problem of a long critical path delay caused by the deep logic depth of the filter due to adder sharing. Furthermore, there is such a disadvantage that they use the transposed direct form (TDF) filter which needs more registers than those of the direct form (DF) filter. In this paper, we present a hybrid structure of a TDF and DF based on the flattened coefficients method so that it can reduce the number of flip‐flops and full‐adders without additional critical path delay. We also propose a resource sharing method and sharing‐pattern searching algorithm to reduce the number of adders without deepening the logic depth. Simulation results show that the proposed structure can save the number of adders and registers by 22 and 26%, respectively, compared to the best one used in the past.     

A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor

To verify three important circuit schemes suitable for DRAMs in mobile applications, a 1.8-V 128-Mb SDRAM was implemented with a 0.15-/spl mu/m technology. To achieve an ideal 33% efficiency, the double boosting pump uses two capacitor's series connection at pumping phase, while they are precharged in parallel. The hybrid folded current sense amplifier together with a novel replica inverter connection improved power and speed performances. Also, a dual-referenced adjustment scheme for a temperature sensor was proposed to allow a very high accuracy in tuning. Without loss in productivity, the implemented dual-referenced searching technique achieved tuning error of less than /spl plusmn/2.5/spl deg/C.     

K- and Q-bands CMOS frequency sources with X-band quadrature VCO

Fully integrated 10-, 20-, and 40-GHz frequency sources are presented, which are implemented with a 0.18-/spl mu/m CMOS process. A 10-GHz quadrature voltage-controlled oscillator (QVCO) is designed to have output with a low dc level, which can be effectively followed by a frequency multiplier. The proposed multipliers generate signals of 20 and 40 GHz using the harmonics of the QVCO. To have more harmonic power, a frequency doubler with pinchoff clipping is used without any buffers or dc-level shifters. The QVCO has a low phase noise of -118.67 dBc/Hz at a 1-MHz offset frequency with a 1.8-V power supply. The transistor size effect on phase noise is investigated. The frequency doubler has a low phase noise of -111.67 dBc/Hz at a 1-MHz offset frequency is measured, which is 7 dB higher than a phase noise of the QVCO. The doubler can be tuned between 19.8-22 GHz and the output is -6.83 dBm. A fourth-order frequency multiplier, which is used to obtain 40-GHz outputs, shows a phase noise of -102.0 dBc/Hz at 1-MHz offset frequency with the output power of -18.0 dBm. A large tuning range of 39.3-43.67 GHz (10%) is observed.     

Highly Customizable All Solution–Processed Polymer Light Emitting Diodes with Inkjet Printed Ag and Transfer Printed Conductive Polymer Electrodes

Inkjet and transfer printing processes are combined to easily form patterned poly(3,4‐ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) films as top anodes of all solution–processed inverted polymer light emitting diodes (PLEDs) on rigid glass and flexible plastic substrates. An adhesive PEDOT:PSS ink is formulated and fully customizable patterns are obtained using the inkjet printing process. In order to transfer the patterned PEDOT:PSS films, adhesion properties at interfaces during multistep transfer printing processes are carefully adjusted. The transferred PEDOT:PSS film on the plastic substrates shows not only a sheet resistance of 260.6 Ω/□ and a transmittance of 92.1% at 550 nm wavelength but also excellent mechanical flexibility. The PLEDs with spin‐coated functional layers sandwiched between the transferred PEDOT:PSS top anodes and inkjet‐printed Ag bottom cathodes are fabricated. The fabricated PLEDs on the plastic substrates show a high current efficiency of 10.4 cd A^?1 and high mechanical stability. It is noted that because both Ag and PEDOT:PSS electrodes can be patterned with a high degree of freedom via the inkjet printing process, highly customizable PLEDs with various pattern sizes and shapes are demonstrated on the glass and plastic substrates. Finally, with all solution process, a 5 × 7 passive matrix PLED array is demonstrated.     

Charge Transportation and Chirality in Liquid Crystalline Helical Network Phases of Achiral BTBT-Derived Polycatenar Molecules

First examples of multichain (polycatenar) compounds, based on the π-conjugated [1]benzothieno[3,2-b]benzothiophene unit are designed, synthesized, and their soft self-assembly and charge carrier mobility are investigated. These compounds, terminated by the new fan-shaped 2-brominated 3,4,5-trialkoxybenzoate moiety, form bicontinuous cubic liquid crystalline (LC) phases with helical network structure over extremely wide temperature ranges (>200 K), including ambient temperature. Compounds with short chains show an achiral cubic phase with the double network, which upon increasing the chain length, is at first replaced by a tetragonal 3D phase and then by a mirror symmetry is broken triple network cubic phase. In the networks, the capability of bypassing defects provides enhanced charge carrier mobility compared to imperfectly aligned columnar phases, and the charge transportation is non-dispersive, as only rarely observed for LC materials. At the transition to a semicrystalline helical network phase, the conductivity is further enhanced by almost one order of magnitude. In addition, a mirror symmetry broken isotropic liquid phase is formed beside the 3D phases, which upon chain elongation is removed and replaced by a hexagonal columnar LC phase.     

Area-efficient correlated double sampling scheme with single sampling capacitor for CMOS image sensors

An area-efficient correlated double sampling (CDS) circuit is proposed. In conventional designs, most of the area of CDS circuits is occupied by two large on-chip sampling capacitors. A new CDS scheme is devised using only one sampling capacitor. The proposed CDS circuit has been successfully realised in a small two column pitch of 7.2 /spl mu/m in a test chip fabricated using 0.18 /spl mu/m CMOS process and has demonstrated fixed pattern noise less than 0.46%.     

Performance of Efficient Signal Detection for LED-ID Systems

In this paper, effects of reader-to-reader interference are investigated for LED identification (LED-ID) system in a multi-reader environment. The LED-ID readers typically use different channels to avoid collision between readers. However, in-channel collision usually happens in terms of interrogation range. A reader-to-reader interference scenario is proposed, and nominal interrogation range of a desired reader is derived from this model. In order to evaluate the LED-ID reader-to-reader interference quantitatively, an efficient detection scheme is proposed and simulated by employing spreading sequence. The spreading sequence is inserted between each user’s frame formats. In the receiver, the desired signal is detected by using correlation among inserted spreading sequences. From simulation results, it is confirmed that the proposed scheme is very effective to enhance reliability of LED-ID communication systems.     

A Rigorous 2D Approximation Technique for 3D Waveguide Structures for BPM Calculations

We propose a rigorous 2D approximation technique for the 3D waveguide structures; it can minimize the well‐known approximation errors of the commonly used effective index method. The main concept of the proposed technique is to compensate for the effective cladding index in the equivalent slab model of the original channel waveguide from the modal effective index calculated by the nonuniform 2D finite difference method. With simulations, we used the proposed technique to calculate the coupling characteristics of a directional coupler by the 2D beam propagation method, and the results were almost exactly the same as the results calculated by the 3D beam propagation method.     

使用集成式负载开关和降压转换器组合 实现更可靠的USB调制解调器设计

在便携电子产品市场,无线网络的出现让人们能够随时随地进行高效的无线通信,而这正是设计便携式电子产品时的首要考虑因素之一。无线调制解调器是一种与无线网络而非电话系统连接的调制解调器。当用户连接无线调制解调器时,实际上就直接连接了无线互联网服务提供商。全球移动通信系统（GlobalSystemforMobile,GSM）和通用分包无线服务（GeneralPacketRadioService,GPRS）无线调制解调器均由uSB的VBUS线供电,提供了一种实现通用式便携设备环境的好方法。不过,这种调制解调器设计也带来了功率管理问题,因为GSM和GPRS发送器需要高达2A的峰值电流,而这却超过了USB电源的最大电流容量。