Ultra-thin high-density LSI packaging substrate for advanced CSPs and SiPs

An ultra-thin high-density LSI packaging substrate, called multi-layer thin substrate (MLTS), is described. It meets the demand for chip scale packages (CSPs) and systems in a package (SiPs) for use in recently developed small portable applications with multiple functions. A high-density build-up structure is fabricated on a Cu plate, which is then removed, leaving only an ultra-thin, high-density multi-layer substrate. MLTS has (1) excellent registration accuracy, which enables higher density and finer pitch patterning due to the use of a rigid, excellent-flatness Cu base plate; (2) a thinner multi-layer structure due to the use of a core-less multi-layer structure; (3) excellent reliability, supported by the use of an aramid-reinforced epoxy resin dielectric layer; and (4) a cost-effective design due to the use of fewer layers fabricated using a conventional build-up process. A prototype high-density CSP (0.4-mm pitch/288 pins/4 rows/10 mm²) was fabricated using a 90-μm-thick MLTS (with a solder resist layer). Testing demonstrated that it had excellent long-term reliability. A prototype ultra-thin, high-density SiP (0.5-mm pitch/225 pins/11 mm²/0.93 mm thick) was also fabricated based on MLTS. MLTS consists of only two conductor layers (total thickness: 90 μm) while an identical-function build-up printed wiring board needs four conductor layers (total thickness: 300 μm). With its thinner core-less multi-layer structure, MLTS enables the fabrication of ultra-thin, high-density SiPs.     

Single-Photon Interference Experiment Over 80 km With a Pulse-Driven Heralded Single-Photon Source

We have conducted a single-photon interference experiment over an 80-km optical fiber using a pulse-driven heralded single-photon source (HSPS). To the best of our knowledge, this is, thus far, the longest distance over which a single-photon interference experiment has been conducted using HSPSs (continuous-wave-pumped or pulse-driven). The effect of the 80-km transmission on the dispersion and fluctuation of polarization are more severe than those in our previous 40-km quantum key distribution (QKD) experiment. We have overcome the difficulties by some fine tunings and low-jitter controlling. By conducting ten consecutive transmission experiments over a total time of 30 min, an average quantum bit-error rate (QBER) of 7.9 plusmn 1.2% has been obtained. This QBER is lower than the threshold QBER of 10.55% which is considered as a limit for unconditional security for the QKD under negligible multiphoton emission.     

Effects of Heavy Element Substitution on Electronic Structure and Lattice Thermal Conductivity of Fe2VAl Thermoelectric Material

By using first-principles cluster calculations, we identified that Ta or W substitution for V is useful for decreasing the lattice thermal conductivity of the Fe₂VAl Heusler alloy without greatly affecting the electron transport properties. It was clearly confirmed that the Fe₂(V_1?x Ta _x )Al_0.95Si_0.05 (x?=?0, 0.025, 0.05), Fe₂(V_0.9?x Ta _x Ti_0.1)Al (x?=?0, 0.10, 0.20), and Fe₂(V_0.9?2x W _x Ti_0.1+x )Al (x?=?0, 0.05, 0.10) alloys indeed possessed large Seebeck coefficient regardless of the amounts of substituted elements, while their lattice thermal conductivity was effectively reduced. As a result of partial substitution of Ta for V, we succeeded in increasing the magnitude of the dimensionless figure of merit of the Heusler phase up to 0.2, which is five times as large as the Ta-free compound.     

A 146-mm/sup 2/ 8-gb multi-level NAND flash memory with 70-nm CMOS technology

An 8-Gb multi-level NAND Flash memory with 4-level programmed cells has been developed successfully. The cost-effective small chip has been fabricated in 70-nm CMOS technology. To decrease the chip size, a one-sided pad arrangement with compacted core architecture and a block address expansion scheme without block redundancy replacement have been introduced. With these methods, the chip size has been reduced to 146 mm/sup 2/, which is 4.9% smaller than the conventional chip. In terms of performance, the program throughput reaches 6 MB/s at 4-KB page operation, which is significantly faster than previously reported and very competitive with binary Flash memories. This high performance has been achieved by the combination of the multi-level cell (MLC) programming with write caches and with the program voltage compensation technique for neighboring select transistors. The read throughput reaches 60 MB/s using 16I/O configuration.     

Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners

Robust porous low-k/Cu interconnects have been developed for 65-nm-node ultralarge-scale integrations (ULSIs) with 180-nm/200-nm pitched lines and 100-nm diameter vias in a single damascene architecture. A porous plasma-enhanced chemical vapor deposition (PECVD)-SiOCH film (k=2.6) with subnanometer pores is introduced into the intermetal dielectrics on the interlayer dielectrics of a rigid PECVD-SiOCH film (k=2.9). This porous-on-rigid hybrid SiOCH structure achieves a 35% reduction in interline capacitance per grid in the 65-nm-node interconnect compared to that in a 90-nm-node interconnect with a fully rigid SiOCH. A via resistance of 9.7 /spl Omega/ was obtained in 100-nm diameter vias. Interconnect reliability, such as electromigration, and stress-induced voiding were retained with interface modification technologies. One of the key breakthroughs was a special liner technique to maintain dielectric reliability between the narrow-pitched lines. The porous surface on the trench-etched sidewall was covered with an ultrathin plasma-polymerized benzocyclobuten liner (k=2.7), thus enhancing interline time-dependent dielectric breakdown reliability. The introduction of a porous material and the control of the sidewall are essential for 65-nm-node and beyond scaled-down ULSIs to ensure high levels of reliability.     

A transceiver PIC for bidirectional optical communication fabricated by bandgap energy controlled selective MOVPE

A transceiver PIC consisting of a DFB-LD, a receiver PD and a Y-shaped branch waveguides is realized by in-plane bandgap energy controlled selective MOVPE. Both active and passive core layers are formed in one step selective growth, and complicated fabrication procedure is no longer required. More than 1 mW fiber coupled power and 7 GHz receiver bandwidth are obtained. The modulation and detection operations at 500 Mb/s are successfully demonstrated.     

Formation of uniform GaAs multi-atomic steps with 20–30 nm periodicity and related structures on vicinal (111)B planes by MBE

We studied morphology of GaAs surfaces and the transport properties of two-dimensional electron gas (2DEG) on vicinal (111)B planes. Multi-atomic steps (MASs) are found on the vicinal (111)B facet grown by molecular beam epitaxy, which will affect electron transport on the facet. We also studied how the morphology of GaAs epilayers on vicinal (111)B substrates depends on growth conditions, especially on the As₄ flux. The uniformity of MASs on the substrates have been improved and smooth surfaces were obtained when the GaAs was grown with high As₄ flux, providing step periodicity of 20 nm. The channel resistance of the 2DEG perpendicular to the MASs is reduced drastically with this smooth morphology. These findings are valuable not only for fabricating quantum devices on the (111)B facets but also those on the vicinal (111)B substrates.     

An experimental 1.5-V 64-Mb DRAM

Low-voltage circuit technologies for higher-density dynamic RAMs (DRAMs) and their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage are presented. A complementary current sensing scheme is proposed to reduce data transmission delay. A speed improvement of 20 ns was achieved when utilizing a 1.5-V power supply. An accurate and speed-enhanced half-V_CC voltage generator with a current-mirror amplifier and tri-state buffer is proposed. With it, a response time reduction of about 1.5 decades was realized. A word-line driver with a charge-pump circuit was developed to achieve a high boost ratio. A ratio of about 1.8 was obtained from a power supply voltage as low as 1.0 V. A 1.28 μm² crown-shaped stacked-capacitor (CROWN) cell was also made to ensure a sufficient storage charge and to minimize data-line interference noise. An experimental 1.5 V 64 Mb DRAM was designed and fabricated with these technologies and 0.3 μm electron-beam lithography. A typical access time of 70 ns was obtained, and a further reduction of 50 ns is expected based on simulation results. Thus, a high-speed performance, comparable to that of 16-Mb DRAMs, can be achieved with a typical power dissipation of 44 mW, one tenth that of 16-Mb DRAMs. This indicates that a low-voltage battery operation is a promising target for future DRAMs     

Perovskite-type oxides La1−xSrxMnO3 for cathode catalysts in direct ethylene glycol alkaline fuel cells

Carbon-supported La_1−xSr_xMnO₃ (LSM/C) was prepared by reversible homogeneous precipitation method, and its catalytic activities for oxygen reduction under the existence of ethylene glycol (EG) were investigated by using rotating disk electrode. LSM/C exhibited the high activity for oxygen reduction irrespective with the presence of EG, indicating that EG is not oxidized by LSM/C at the cathode side in the present system. Consequently, LSM/C can serve as a cathode catalyst in alkaline direct alcohol fuel cells with no crossover problem. Performance test for fuel cells operation also supported these results and showed cathodic polarization curves were not affected by the concentration of EG supplied to anode even at 5 mol dm⁻³.