Modified planar inverted F antenna

The design of a modified planar inverted F antenna (PIFA) which is more compact (antenna length <λ₀/8 and antenna height <0.01 λ₀) and has a much wider antenna bandwidth (greater than 10 times that of a simple PIFA) is demonstrated. The reduction in antenna length is achieved by meandering the radiating patch, while the enhanced bandwidth with low antenna height is obtained using a chip-resistor load in place of the shorting post. A typical design of the modified PIFA in the 800 MHz band has been implemented, and experimental results are presented and discussed     

Single-feed dual-band circularly polarised microstrip antenna

A novel technique for obtaining dual-band circular polarisation (CP) radiation of a single-feed circular microstrip antenna is proposed and demonstrated. By embedding two pairs of arc-shaped slots of proper lengths close to the boundary of a circular patch, and protruding one of the arc-shaped slots with a narrow slot, the circular microstrip antenna can perform dual-band CP radiation using a single probe feed. Details of the antenna design and experimental results are presented     

Small slot-coupled circularly-polarised microstrip antenna withmodified cross-slot and bent tuning-stub

A novel design of small slot-coupled circularly-polarised circular microstrip antenna with a modified cross-slot cut in the patch and a bent tuning-stub aligned along the patch boundary is proposed and experimentally studied. Results show that, for fixed circular polarisation (CP) operation, the antenna proposed can have an antenna size reduction of ~80%, as compared to a regular-size CP design. The significant size reduction of the proposed antenna is due to the novel modified cross-slot cut in the patch, and CP operation is obtained using a bent tuning-stub incorporating a properly oriented coupling-slot in the ground plane of the microstrip feed line     

Circularly polarised microstrip antenna with a tuning stub

A simple circular polarisation (CP) design of microstrip antennas using a tuning stub is proposed and studied. It is also demonstrated that, by applying this CP design method to a circular microstrip patch with a cross slot having equal slot lengths, a compact circularly-polarised microstrip antenna can easily be implemented, with much more relaxed manufacturing tolerances as compared to the case of using a cross slot of unequal slot lengths. Details of the antenna designs are described, and experimental results are presented and discussed     

Bandwidth enhancement of inset-microstrip-line-fedequilateral-triangular microstrip antenna

By embedding a pair of properly-bent narrow slots in an equilateral-triangular microstrip patch, broadband operation of microstrip antennas with an inset microstrip-line feed can be achieved. With the proposed antenna design, the impedance bandwidth can be as large as ~3.0 times that of a corresponding simple triangular microstrip antenna. Some simple design rules for the proposed antenna have also been determined experimentally. The design rules and experimental results are presented and discussed     

A study of tilt angle effect on Halo PMOS performance

The Halo structure is usually adopted in deep submicrometer MOS devices for punchthrough prevention. The tilt angle of the Halo implant determines the dopant distribution which induces anti-punchthrough operation. In this paper, we investigate the impact of the tilt angle on the Halo PMOS device performance via two-dimensional (2D) simulations. We find that the ratio of on-current to off-current is constant for all tilt angles of Halo implant, implying an equivalent DC performance for all tilt angles. The equivalence can be traced back to a self compensation between the body factor and source resistance. The result implies that a low tilt angle should be adopted for Halo devices, for it gives a small threshold voltage and thus a high noise margin. The methodology used in analyzing body factor and source resistance can also be applied to analyze other devices.     

A phenomenon of charge trapping saturation induced by rapid thermal annealing

In this paper, we investigate the impact of the rapid thermal annealing (RTA) temperature on the performance degradation of NMOS devices, due to hot electrons. Our results indicate that RTA with a higher temperature achieves a higher interface barrier and induces a greater initial positive trapped charge. We observe a new three-section degradation phenomenon during DC stress at a low RTA temperature of 875°C, along with the discovery of a non-monotonic substrate current degradation which finally saturates. We note that the non-monotonicity is induced by a trapped charge polarity change, and the saturation is induced by a progression of an injected charge pocket toward the channel. This study provides an insight into the analysis of device degradation vs the RTA temperature, and should be useful for reliability optimization in process integration.     

Optimum filter banks for signal decomposition and its applicationin adaptive echo cancellation

The application of multirate filter banks in echo cancellation is investigated. The multiresolution algorithm is used to decompose the received sampling sequence into a number of components, and then, an adaptive algorithm is applied to cancel the echo in the received signal. In this paper, the performance of this method is discussed, from which optimal conditions for echo cancellation are established for the design of wavelet packet multiresolution decomposition. An efficient algorithm for designing such a set of optimal discrete filter banks is developed. The cases of optimal in-band and adjacent-band adaptive filtering are examined. Experimental results showed that the use of optimally designed multiresolution filter banks coupled with in-band or adjacent-band adaptive filtering is much more effective than the employment of commonly used wavelet filter banks. Furthermore, the use of the adjacent-band adaptive filtering algorithm has superior performance compared with that of the in-band filtering     

High speed flow visualization of a closed loop pulsating heat pipe

We provide the high speed flow visualization results for the closed loop pulsating heat pipes (PHPs). It is identified that there exists the bulk circulation flow which lasts longer and the local flow direction switch flow. The bubble displacements and velocities do display the sine oscillation waves but the local oscillation waves were superimposed with short periods and small oscillation amplitudes. Distinct with the methanol PHP, the water PHP has quasi-rectangular shape for the bubble displacements, behaving the periodic stationary-fast movement characteristics. Dispersed bubbles, vapor plugs and the transition flow patterns from the dispersed bubbles to the vapor plugs are the major flow patterns in PHP. Long vapor plugs are only observed for the methanol PHP, not observed in the water PHP, due to the vapor plug deformation and breakup mechanism, which was analyzed in the present paper. Bubble sizes have quasi-fixed distributions versus time over the entire PHP, but have unsymmetry distributions among various tubes. The complicated combined effects of bubble nucleation, coalescence and condensation are responsible for the oscillation flow in PHP.     

Optimization of on-chip ESD protection structures for minimal parasitic capacitance

Diodes are key components in on-chip electrostatic discharge (ESD) protection design. As the operating frequency of the microchip being protected against the ESD continues to increase, the parasitic capacitance associated with the diodes in the ESD structure starts to impose problems for RF operation. This paper presents a systematic approach to optimize the diode structure for minimal parasitic capacitance based on the requirements of breakdown voltage and heat dissipation. Device simulator Atlas with mix-mode simulation capability is calibrated against measurement data and used to carry out the optimization. An optimized diode structure with a parasitic capacitance of less than 30 fF at an operating frequency of 10 GHz and ESD charging voltage of 1 kV has been suggested. Furthermore, a case study to implement and optimize the ESD protection structure based on an existing 0.13-μm CMOS technology has been presented and verified.