Distributed Arithmetic based Split-Radix FFT

In this paper we have designed a Split-radix type FFT unit without using multipliers. All the complex multiplications required for this type of FFT are implemented using Distributed Arithmetic (DA) technique. A method is incorporated to overcome the result overflow problem introduced by DA method. Proposed FFT architecture is implemented in 180 nm CMOS technology at a supply voltage of 1.8 V.     

Miniaturised two-stage balanced Ku-band CPW MMIC amplifier using impedance transforming couplers

A two-stage balanced Ku-band coplanar waveguide amplifier design is presented which has been miniaturised by using impedance transforming couplers which considerably reduce the required matching networks to the MESFETs. The amplifier, measuring only 2*1.7 mm/sup 2/, exhibits a gain of 13.7 dB with less than +or-0.2 dB of ripple over the range 14-16 GHz.<>     

Direct analytical solution for the electric field distribution atthe conductor surfaces of coplanar waveguides

A new analytical method of evaluating the electric field distribution across the conductor surfaces of coplanar waveguides (CPWs) is presented. Here, a series of conformal mappings are used to transform the CPW's geometry and field distribution into a uniform image domain, to facilitate a direct field solution. The cumulative electric flux distribution across each conductor surface within the dielectric substrate is studied, and its effects on coupling and propagation modes are described. Direct solutions for the quasi-static normal electric field components are presented together with their graphical representations. Numerical computations show how the total electric flux terminating on the CPW's conductor surfaces varies in terms of the CPW's geometry and substrate parameters     

Performance evaluation of a teletext system

Four parameters are defined to measure the performance of a teletext system, namely, the probability of delivering a message within specified time, the transmission efficiency, the average number of errors per page, and the throughput. Each of them is derived and computational results are presented taking the UK teletext system as an example. These parameters are compared in their ability to characterize the performance of the teletext system     

Scaling planar silicon devices

The generation-over-generation scaling of critical CMOS technology parameters is ultimately bound by nonscalable limitations, such as the thermal voltage and the elementary electronic charge. Sustained improvement in performance and density has required the introduction of new device structures and materials. Partially depleted SOI, a most recent MOSFET innovation, has extended VLSI performance while introducing unique idiosyncrasies. Fully depleted SOI is one logical extension of this device design direction. Gate dielectric tunneling, device self-heating, and single-event upsets present developers of these next-generation devices with new challenges. Strained silicon and high-permittivity gate dielectric are examples of new materials that will enable CMOS developers to continue to deliver device performance enhancements in the sub-100 nm regime.     

Research issues in developing compact pulsed power for high peak power applications on mobile platforms

Pulsed power is a technology that is suited to drive electrical loads requiring very large power pulses in short bursts (high-peak power). Certain applications require technology that can be deployed in small spaces under stressful environments, e.g., on a ship, vehicle, or aircraft. In 2001, the U.S. Department of Defense (DoD) launched a long-range (five-year) Multidisciplinary University Research Initiative (MURI) to study fundamental issues for compact pulsed power. This research program is endeavoring to: 1) introduce new materials for use in pulsed power systems; 2) examine alternative topologies for compact pulse generation; 3) study pulsed power switches, including pseudospark switches; and 4) investigate the basic physics related to the generation of pulsed power, such as the behavior of liquid dielectrics under intense electric field conditions. Furthermore, the integration of all of these building blocks is impacted by system architecture (how things are put together). This paper reviews the advances put forth to date by the researchers in this program and will assess the potential impact for future development of compact pulsed power systems.     

Levinson-like and Schur-like fast algorithms for solvingblock-slanted Toeplitz systems of equations arising in wavelet-basedsolution of integral equations

The Wiener-Hopf integral equation of linear least-squares estimation of a wide-sense stationary random process and the Krein integral equation of one-dimensional (1-D) inverse scattering are Fredholm equations with symmetric Toeplitz kernels. They are transformed using a wavelet-based Galerkin method into a symmetric “block-slanted Toeplitz (BST)” system of equations. Levinson-like and Schur-like fast algorithms are developed for solving the symmetric BST system of equations. The significance of these algorithms is as follows. If the kernel of the integral equation is not a Calderon-Zygmund operator, the wavelet transform may not sparsify it. The kernel of the Krein and Wiener-Hopf integral equations does not, in general, satisfy the Calderon-Zygmund conditions. As a result, application of the wavelet transform to the integral equation does not yield a sparse system matrix. There is, therefore, a need for fast algorithms that directly exploit the (symmetric block-slanted Toeplitz) structure of the system matrix and do not rely on sparsity. The first such O(n²) algorithms, viz., a Levinson-like algorithm and a Schur (1917) like algorithm, are presented. These algorithms are also applied to the factorization of the BST system matrix. The Levinson-like algorithm also yields a test for positive definiteness of the BST system matrix. The results obtained are directly applicable to the problem of constrained deconvolution of a nonstationary signal, where the locations of the smooth regions of the signal being deconvolved are known a priori     

Effects of transverse doping variations on the transient responseof silicon avalanche shaper devices

Two-dimensional (2-D) drift-diffusion simulations were performed to study the transient response of silicon avalanche shaper (SAS) devices that are used in high-power switching and pulse sharpening applications. The role of transverse doping variations on the transient device response has been studied. Our results clearly reveal a potential for filamentary current conduction. The filamentation, however, is shown to be strongly dependent on the transverse doping characteristics, and hence in principle, could he tailored     

Ultra-Thin Si<Subscript>1−<Emphasis Type="Italic">x</Emphasis></Subscript>Ge<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript> Dislocation Blocking Layers for Ge/Strained Si CMOS Devices

We demonstrate ultra-thin (<150 nm) Si_1−x Ge _x dislocation blocking layers on Si substrates used for the fabrication of tensile-strained Si N channel metal oxide semiconductor (NMOS) and Ge P channel metal oxide semiconductor (PMOS) devices. These layers were grown using ultra high vacuum chemical vapor deposition (UHVCVD). The Ge mole fraction was varied in rapid, but distinct steps during the epitaxial layer growth. This results in several Si_1−x Ge _x interfaces in the epitaxially grown material with significant strain fields at these interfaces. The strain fields enable a dislocation blocking mechanism at the Si_1−x Ge _x interfaces on which we were able to deposit very smooth, atomically flat, tensile-strained Si and relaxed Ge layers for the fabrication of high mobility N and P channel metal oxide semiconductor (MOS) devices, respectively. Both N and P channel metal oxide semiconductor field effect transister (MOSFETs) were successfully fabricated using high-k dielectric and metal gates on these layers, demonstrating that this technique of using ultra-thin dislocation blocking layers might be ideal for incorporating high mobility channel materials in a conventional CMOS process.