Design of Engineered Elastomeric Substrate for Stretchable Active Devices and Sensors

In the field of flexible electronics, emerging applications require biocompatible and unobtrusive devices, which can withstand different modes of mechanical deformation and achieve low complexity in the fabrication process. Here, the fabrication of a mesa‐shaped elastomeric substrate, supporting thin‐film transistors (TFTs) and logic circuits (inverters), is reported. High‐relief structures are designed to minimize the strain experienced by the electronics, which are fabricated directly on the pillars' surface. In this design configuration, devices based on amorphous indium‐gallium‐zinc‐oxide can withstand different modes of deformation. Bending, stretching, and twisting experiments up to 6 mm radius, 20% uniaxial strain, and 180° global twisting, respectively, are performed to show stable electrical performance of the TFTs. Similarly, a fully integrated digital inverter is tested while stretched up to 20% elongation. As a proof of the versatility of mesa‐shaped geometry, a biocompatible and stretchable sensor for temperature mapping is also realized. Using pectin, which is a temperature‐sensitive material present in plant cells, the response of the sensor shows current modulation from 13 to 28 °C and functionality up to 15% strain. These results demonstrate the performance of highly flexible electronics for a broad variety of applications, including smart skin and health monitoring.     

Single Filter Frequency Masking High-Speed Recursive Digital Filters

For recursive filter the maximal sample frequency is bounded by the recursive loops in the filter. [In this paper, it is understood that recursive filters are infinite-length impulse response (IIR) filters.] In this work, a filter structure based on the use of the frequency masking approach is presented that increases the maximal sample frequency for narrowband and wideband filters by introducing more delay elements in the recursive loops. By using identical subfilters (except for the periods), the subfilters can be mapped using folding to a single pipeline/interleaved arithmetic structure yielding an area-efficient implementation. The filters are potentially suitable for low-power implementation by using power supply voltage scaling techniques. In this work, the design of the filters is discussed and estimations of the ripples are derived. Two examples show the viability of the proposed method.     

Kinematics of the heart: strain-rate imaging from time-resolved three-dimensional phase contrast MRI

A four-dimensional mapping (three spatial dimensions + time) of myocardial strain-rate would help to describe the mechanical properties of the myocardium, which affect important physiological factors such as the pumping performance of the ventricles. Strain-rate represents the local instantaneous deformation of the myocardium and can be calculated from the spatial gradients of the velocity field. Strain-rate has previously been calculated using one-dimensional (ultrasound) or two-dimensional (2-D) magnetic resonance imaging) techniques. However, this assumes that myocardial motion only occurs in one direction or in one plane, respectively. This paper presents a method for calculation of the time-resolved three-dimensional (3-D) strain-rate tensor using velocity vector information in a 3-D spatial grid during the whole cardiac cycle. The strain-rate tensor provides full information of both magnitude and direction of the instantaneous deformation of the myocardium. A method for visualization of the full 3-D tensor is also suggested. The tensors are visualized using ellipsoids, which display the principal directions of strain-rate and the ratio between strain-rate magnitude in each direction. The presented method reveals the principal strain-rate directions without a priori knowledge of myocardial motion directions.     

Performance evaluation of DCCP: A focus on smoothness and TCP-friendliness

Recent years have seen dramatic increases of the use of multimedia applications on the Internet, which typically either lack congestion control or use proprietary congestion control mechanisms. This can easily cause congestion collapse or compatibility problems. Datagram Congestion Control Protocol (Dccp) fills the gap betweenUdp andTcp, featuring congestion control rather than reliability for packet-switched rich content delivery with high degree of flexibility. We present aDccp model designed and implemented withOpnet Modeler, and the experiments and evaluation focused on largely the smoothness of the data rates, and the fairness between concurrentDccp flows andTcp flows. We foundDccp-ccid3 demonstrates stable data rates under different scenarios, and the fairness betweenDccp andTcp is only achieved under certain conditions. We also validated that the throughput ofDccp-Ccid3 is proportional to the average packet size, and relatively fixed packet size is critical for the optimal operation ofDccp. Problems in the slow start phase and insufficient receiver buffer size were identified and we hereby proposed solutions on this.     

Cryptanalysis of MD2

This paper considers the hash function MD2 which was developed by Ron Rivest in 1989. Despite its age, MD2 has withstood cryptanalytic attacks until recently. This paper contains the state-of-the-art cryptanalytic results on MD2, in particular collision and preimage attacks on the full hash function, the latter having complexity 2⁷³, which should be compared to a brute-force attack of complexity 2¹²⁸.     

RTD/CMOS nanoelectronic circuits: thin-film InP-based resonanttunneling diodes integrated with CMOS circuits

The combination of resonant tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) silicon circuitry can offer substantial improvement in speed, power dissipation, and circuit complexity over CMOS-only circuits. We demonstrate the first integrated resonant tunneling CMOS circuit, a clocked 1-bit comparator with a device count of six, compared with 21 in a comparable all-CMOS design. A hybrid integration process is developed for InP-based RTDs which are transferred and bonded to CMOS chips. The prototype comparator shows sensitivity in excess of 10⁶ VIA, and achieves error-free performance in functionality testing. An optimized integration process, under development, can yield high-speed, low power circuits by lowering the high parasitic capacitance associated with the prototype circuit     

A low-power 2nd-order CT delta-sigma modulator with a single operational amplifier

We present a 2nd-order 4-bit continuous-time (CT) delta-sigma modulator (DSM) employing a 2nd-order loop filter with a single operational amplifier. This choice strongly reduces the power consumption, since operational amplifiers are the most power hungry blocks in the DSM. The DSM has been implemented in a 65 nm CMOS process, where it occupies an area of \(0.08\,\hbox {mm}^2\) . It achieves an SNDR of 64 dB over a 500 kHz signal bandwidth with an oversampling ratio of 16. The power consumption is \(76\,\upmu \hbox {W}\) from a 800 mV power supply. The DSM figure-of-merit is 59 fJ/conversion. The CT DSM is well suited for the receiver of an ultra-low-power radio.     

Enhancing the Selectivity and Transparency of the Electron Contact in Silicon Heterojunction Solar Cells by Phosphorus Catalytic Doping

An intrinsic hydrogenated amorphous silicon (a-Si:H(i)) film and a doped silicon film are usually combined in the heterojunction contacts of silicon heterojunction (SHJ) solar cells. In this work, a post-doping process called catalytic doping (Cat-doping) on a-Si:H(i) is performed on the electron selective side of SHJ solar cells, which enables a device architecture that eliminates the additional deposition of the doped silicon layer. Thus, a single phosphorus Cat-doping layer combines the functions of two other layers by enabling excellent interface passivation and high carrier selectivity. The overall thinner layer on the window side results in higher spectral response at short wavelengths, leading to an improved short-circuit current density of 40.31 mA cm⁻² and an efficiency of 23.65% (certified). The cell efficiency is currently limited by sputter damage from the subsequent transparent conductive oxide fabrication and low carrier activation in the a-Si:H(i) with Cat-doping. Numerical device simulations show that the a-Si:H(i) with Cat-doping can provide sufficient field effect passivation even at lower active carrier concentrations compared to the as-deposited doped layer, due to the lower defect density.     

Structural Aspects of P2-Type Na0.67Mn0.6Ni0.2Li0.2O2 (MNL) Stabilization by Lithium Defects as a Cathode Material for Sodium-Ion Batteries

A known strategy for improving the properties of layered oxide electrodes in sodium-ion batteries is the partial substitution of transition metals by Li. Herein, the role of Li as a defect and its impact on sodium storage in P2-Na_0.67Mn_0.6Ni_0.2Li_0.2O₂ is discussed. In tandem with electrochemical studies, the electronic and atomic structure are studied using solid-state NMR, operando XRD, and density functional theory (DFT). For the as-synthesized material, Li is located in comparable amounts within the sodium and the transition metal oxide (TMO) layers. Desodiation leads to a redistribution of Li ions within the crystal lattice. During charging, Li ions from the Na layer first migrate to the TMO layer before reversing their course at low Na contents. There is little change in the lattice parameters during charging/discharging, indicating stabilization of the P2 structure. This leads to a solid-solution type storage mechanism (sloping voltage profile) and hence excellent cycle life with a capacity of 110 mAh g^-1 after 100 cycles. In contrast, the Li-free compositions Na_0.67Mn_0.6Ni_0.4O₂ and Na_0.67Mn_0.8Ni_0.2O₂ show phase transitions and a stair-case voltage profile. The capacity is found to originate from mainly Ni³⁺/Ni⁴⁺ and O^2-/O^2-δ redox processes by DFT, although a small contribution from Mn⁴⁺/Mn⁵⁺ to the capacity cannot be excluded.