High-performance and power-efficient CMOS comparators

Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques.     

Popular biorthogonal wavelet filters via a lifting scheme and its application in image compression

A technique using a lifting scheme is presented for constructing compactly supported wavelets whose coefficients are composed of free variables locating in an interval. An efficient approach-based wavelet for image compression is developed by selecting the coefficients of the 9-7 wavelet filter and associated lifting scheme. Furthermore, the rationalised coefficients wavelet filter that can be implemented with simple integer arithmetic is achieved and its characteristic is close to the well known original irrational coefficients 9-7 wavelet filters developed by A. Cohen et al. (Commun. Pure Appl. Maths., vol.45, no.1, p.485-560, 1992). To reduce the computational cost of image coding applications further, an acceleration technique is proposed for the lifting steps. Software and hardware simulations show that the new method has very low complexity, and simultaneously preserves the high quality of the compressed image.     

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

地震多次波压制方法技术应用研究

辽河盆地西部凹陷地质条件复杂，地震波场中多次波较发育，受其影响，主要目的层反射波干涉现象较严重，有效波难以识别，总体信噪比不高，给构造及岩性解释造成困难。对三维地震资料的处理研究表明，采用预测反褶积、F—K域多次波衰减技术及近道内切法等相结合的方法压制多次波是一种有效的途径。从资料处理效果看，剖面质量明显得到改善，证明该组合去噪技术是切实可行的。     

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.     

Effects of genotype and treatment on the antioxidant activity of sweet potato in Taiwan

Six genotypes of sweet potato commercially available in Taiwan, including TNG57, TNG66, TNG68, TYY1, RP and WP, were used as samples in this study of the effects of steaming and kneading with pre-steaming treatments on the antioxidant components and antioxidant properties of methanolic extracts. Steam treatment increased the total phenols contents of all genotypes (2–13 times), flavonoids content of RP (1.3 times) and anthocyanins contents of RP and WP (5–6 times). Steam treatment also increased the reducing power and scavenging DPPH radical effect of sweet potato flours. For the methanolic extracts of steamed and kneaded flours, reducing powers were 0.02–1.70 at 5.0 mg ml⁻¹ and the scavenging effects on DPPH radicals were 19–92% at 2.5 mg ml⁻¹. Both showed the order of RP > WP > TYY1 and TNG66 > TNG57 and TNG68. However, the chelating effect of the six genotypes at 1.0 mg ml⁻¹ ranged from 50% to 73%. Contents of total phenols, flavonoids, and anthocyanins of sweet potato flours were significantly positively correlated with the reducing power and scavenging DPPH radical effects. After steaming and kneading treatments, RP showed the highest increase in the contents of total phenols, flavonoids and anthocyanins among the six genotypes studied.     

"十一五"规划国家级重点通信项目

《信息产业科技发展“十一五”规划》提出设立部分重大项目,力争实现重点突破,形成一批具有自主知识产权的核心技术和创新产品,打造较为完整的产业链,形成世界一流的产业群。这其中,与通信相关的重点项目主要有:宽带无线移动通信、下一代网络、家庭网络、智能终端、数字电视等。本部分将对我国在以上领域的现状、项目的具体内容和目标、实现这些目标的具体计划以及相关厂商在各领域的努力和成绩进行介绍。     

基于USB总线的虚拟频谱分析仪设计

文章详细介绍了基于USB总线的虚拟频谱分析仪的设计过程。该仪器使用嵌入式混合处理器MC56F8323来实现动态信号的实时采集、频谱分析和数字滤波等功能。处理结果由USB2．0接口芯片CY7C68013上传至PC机．以完成数据显示、存储、绘制图形等功能。其中，CY7C68013工作于Slave FIFO模式，以实现与MC56F8323间的数据传输。该系统可同时对两路动态信号进行实时谱分析，每路采样频率高选500kHz。     

砾岩储层精细描述中标准测井资料的应用

克拉玛依油田七区的标准测井资料是指使用标准电极系视电阻率测井、自然电位测井和井径测井,以相同的1:500深度比例尺及相同的横向比例进行测井作业所取得的资料.这种资料本来并不具备定量解释储层孔隙度和含油饱和度的能力,但这种资料占该区测井资料总量的比率高达34%.利用标准电极系视电阻率资料和岩心分析资料建立了视电阻率-岩性图版,利用自然电位减小系数α和岩心孔隙度分析资料φ建立了α-φ图版,根据综合测井资料求出标准测井视电阻率校正系数,进而确定了饱和度计算方程的参数.与相应的综合测井资料计算结果相对比,用该方法得到的孔隙度平均绝对误差及相对误差分别为1.85%和11.88%;含油饱和度平均绝对误差及相对误差分别为9.08%和24.75%.将该方法有选择地应用到该区砾岩储层精细描述研究中,弥补了缺乏综合测井资料无法进行测井储层评价及参数研究的缺陷.