Development of an end-point detector for parylene deposition process

Parylene is an emerging material for MEMS. It is an organic material that is grown by using the chemical vapor deposition method at room temperature. The deposition thickness is commonly controlled by the amount of solid-phase dimer loaded in a sublimation chamber. In a conventional deposition machine, the end point of the process is designated by the moment the dimer is exhausted. However, this end-of-process criterion does not offer precise, repeatable control of film thickness. We present the results of the development of an in situ end-point detector for a Parylene chemical vapor deposition process. The detector is based on the thermal transfer principle and can be implemented on commercial parylene deposition systems with minimal system modification. Such a sensor enables a user to stop the deposition when a targeted thickness is reached. The end point detector is very simple to implement on existing parylene deposition systems. A series of such sensors with different target deposition thickness would allow extraction of the actual deposition rate within a deposition run.     

On the possibility of determining internal wave characteristics from the ray arrival time distribution in an underwater sound channel under conditions of Ray Chaos

We describe the simplest mechanism of cluster structure formation in the timefront of an acoustic signal propagating in a submerged channel under ray chaos conditions. It is shown that this cluster structure is related to the phase space structure. This relation allows, in principle, the characteristics of an inhomogeneous medium to be determined from the timefront shape parameters. As an example, the period of inhomogeneity is calculated for a periodic perturbation in the sound velocity caused by an internal wave propagation.     

A digital architecture for support vector machines: theory, algorithm, and FPGA implementation

In this paper, we propose a digital architecture for support vector machine (SVM) learning and discuss its implementation on a field programmable gate array (FPGA). We analyze briefly the quantization effects on the performance of the SVM in classification problems to show its robustness, in the feedforward phase, respect to fixed-point math implementations; then, we address the problem of SVM learning. The architecture described here makes use of a new algorithm for SVM learning which is less sensitive to quantization errors respect to the solution appeared so far in the literature. The algorithm is composed of two parts: the first one exploits a recurrent network for finding the parameters of the SVM; the second one uses a bisection process for computing the threshold. The architecture implementing the algorithm is described in detail and mapped on a real current-generation FPGA (Xilinx Virtex II). Its effectiveness is then tested on a channel equalization problem, where real-time performances are of paramount importance.     

Memory of Distributed Computer Systems: Distinctive Features of Their Architectural-Structural Organization and Use

Distinctive features of architectural-structural organization and use of memory networks are considered with the aim of choosing an optimal configuration in designing distributed computer systems.     

Differentially coherent code acquisition in the MIMO-aided multi-carrier DS-CDMA downlink

Both differentially coherent and non-coherent code acquisition schemes designed for the multiple-input multiple-output (MIMO)-aided multi-carrier (MC)-DS-CDMA downlink are analysed, when communicating over uncorrelated Rayleigh channels. The attainable mean acquisition time (MAT) performance is studied as a function of both the number of multiple transmit/multiple receive antennas and that of the number of subcarriers. It is demonstrated that in contrast to the expectations, when the number of multiple transmit antennas and/or that of the subcarriers is increased in both the differentially coherent and the non-coherent code acquisition scenarios, the achievable MAT deteriorates over the entire signal-to-interference plus noise ratio (SINR) per chip (E_c/I_o) range considered, except for the scenario of single-carrier (SC)-DS-CDMA using P = 2 transmit antennas and R = 1 receive antenna. As expected, the degree of performance degradation depends upon the specific scheme and the E_c/I_o ratio considered, although paradoxically, the correctly synchronised MIMO-aided system is capable of attaining its target bit error ratio performance at reduced SINR values.     

Synchronised carrier-based SVPWM signal generation scheme for the entire modulation range extending up to six-step mode using the sampled amplitudes of reference phase voltages

The issues in synchronised implementation of space vector-based pulse width modulation (SVPWM) signal generation are addressed on a conventional DSP platform. With the present day digital signal processors (DSPs) with clock over 10 MHz, it is possible to include additional tasks for synchronisation in the interrupt service routine (ISR). Also, the task of the synchronisation can be easily accommodated within the same ISR without disturbing the time critical pulse width modulation (PWM) operation. The authors systematically present the additional software requirements to determine the time period proportional to the half carrier switching time interval that is required for the synchronisation. First, the DSP implementation of the conventional multi-level SVPWM based on the sampled amplitudes of reference voltages is presented and then the additional requirements to maintain the PWM in synchronisation are discussed. The simulation results as well as experimental results are presented for a five-level PWM signal generation. A five-level inverter configuration, using a 1.5 kW open-end winding induction motor drive, is used for experimentally verifying the SVPWM     

Hybrid finite-element method for discretising cylindrically symmetric parts in electrotechnical models

In many technical devices such as transformers and electrical machines, large differences in geometric dimensions are observed. As a consequence, the generation of a 3D computational grid for the whole device leads to unacceptably large numbers of elements or can even fail. In addition to the commonly applied cartesian or cylindrical symmetries of the overall geometry, the model can be subdivided into parts featuring translational or cylindrical symmetries. Such parts are discretised separately, accounting for the local symmetry, and are then combined with the surrounding 3D model. Excitations and boundary conditions of the submodels are not necessarily symmetric but are expected to be smooth in the direction of the symmetry. Then, the field distribution at the interface is well approximated by a set of spectral elements along the dimension of symmetry. Coupling between the model parts is carried out by means of Lagrange multipliers. A single-phase transformer with thin insulation sheets is taken as an example to illustrate the proposed hybrid discretisation. The cross-section of the cylindrically symmetric part containing thin sheets, is represented by a fine 2D finite-element mesh so that all the geometrical details can be resolved, and the rest of the structure is discretised by a 3D mesh. Nevertheless, a fully 3D field distribution is calculated in all model parts. Only a small number of harmonic functions is needed to account for the azimuthal field variation at the cylindrical interface. Hence, the number of unknowns in the numerical model is reduced significantly, while a high level of accuracy is maintained     

Effect of spontaneous polarization on the energy levels in quantum wells formed at the contact between cubic and noncubic silicon carbide polytypes

We have studied the effect of spontaneous polarization, which is inherent in noncubic silicon carbide (SiC) polytypes, on the characteristics of quantum wells (QWs) formed in the cubic region at the heterojunction. The analysis is performed for various QW models, including triangular, parabolic, and exponential. Conditions for the appearance of a two-dimensional electron gas at the interface are briefly discussed.     

Microhardness of silicon layers grown by liquid phase epitaxy

The microhardness of silicon epilayers grown from Sn fluxes is found to be lower than that of the silicon substrates and to significantly depend on the crystallographic orientation of the substrates. The microhardness values follow a Gaussian distribution in all of the epilayers. Unintentional impurities are shown to have a significant effect on the microhardness of the epilayers. The addition of ytterbium to the high-temperature solution reduces the microhardness of the epilayers.