All-active monolithic InP-based HBT VCO with tunable HEMT inductor

A novel HEMT-HBT VCO is presented; it is the first all-active analogue VCO demonstrated using InP HEMT-HBT integrated MMIC technology. The MMIC monolithically integrates an InP common-collector HBT oscillator with a tunable InP HEMT active inductor using selective MBE. The novel HEMT-HBT VCO can provide performance advantages over analogue VCOs such as the multi-vibrator, and has direct implications for high speed clock recovery circuits needed in InP based optoelectronic IC applications     

Formation of a step-free InAs quantum well selectively grown on a GaAs (111)B substrate

We investigated the possibility of forming a step-free quantum well structure. A step-free InAs monolayer was grown on a selectively grown mesa by controlling surface phases with in-situ monitoring of surface photo-absorption. We selectively grew a GaAs buffer at 800°C and cooled the sample keeping the (2×2)-like As stabilized surface. Atomic force microscopy (AFM) observation demonstrated that fully step-free surfaces were formed on the 8 μm wide mesa. Then, a monolayer-thick InAs was formed on this step-free surface and this InAs layer was capped by GaAs under the (2×2)-like condition. The quantum level of the step-free InAs layer was evaluated by spatially resolved photoluminescence (μPL) measurement. Uniform PL intensity and the lack of a double layer peak indicated the formation of a step-free InAs quantum well, which was in good agreement with AFM observation.     

A high-speed, low-power bipolar digital circuit for Gb/s LSI's:current mirror control logic

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits. This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF) and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF)     

Nitrogen Doping Effect in a-Ge: H Films Due To High Hydrogen Dilution

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DNA Computing Boosted by a Cationic Copolymer

The huge information storage capability of DNA and its ability to self‐assemble can be harnessed to enable massively parallel computing in a small space. DNA‐based logic gates are designed that rely on DNA strand displacement reactions; however, computation is slow due to time‐consuming DNA reassembly processes and prone to failure as DNA is susceptible to degradation by nucleases and under certain solution conditions. Here, it is shown that the presence of a cationic copolymer boosts the speed of DNA logic gate operations that involve multiple and parallel strand displacement reactions. Two kinds of DNA molecular operations, one based on a translator gate and one on a seesaw gate, are successfully enhanced by the copolymer without tuning of computing conditions or DNA sequences. The copolymer markedly reduces operation times from hours to minutes. Moreover, the copolymer enhances nuclease resistance.     

An image analyzing system using an artificial neural network forevaluating the parenchymal echo pattern of cirrhotic liver and chronichepatitis

To objectively evaluate the parenchymal echo pattern of cirrhotic liver and chronic hepatitis, the authors applied an image analyzing system (IAS) using a neural network. Autopsy specimens in a water tank (n=13) were used to examine the relationship between the diameter of the regenerative nodule and the coarse score (CS) calculated by IAS. CS was significantly correlated with the diameter of the regenerative nodule (p<0.0001, r=0.966). CS is considered to be useful for evaluating the coarseness of the parenchymal echo pattern     

Gain-flattened tellurite-based EDFA with a flat amplificationbandwidth of 76 nm

We describe a tellurite-based Er³⁺-doped fiber amplifier (EDFA) with a flat amplification bandwidth of 76 nm and a noise figure of less than 7 dB. Furthermore, a parallel-type amplifier composed of this EDFA and a 1.45-μm-band Tm³⁺-doped fluoride fiber amplifier achieved a flat amplification bandwidth of 113 nm     

Feature selection by analyzing class regions approximated byellipsoids

In their previous work, the authors have developed a method for selecting features based on the analysis of class regions approximated by hyperboxes. They select features analyzing class regions approximated by ellipsoids. First, for a given set of features, each class region is approximated by an ellipsoid with the center and the covariance matrix calculated by the data belonging to the class. Then, similar to their previous work, the exception ratio is defined to represent the degree of overlaps in the class regions approximated by ellipsoids. From the given set of features, they temporally delete each feature, one at a time, and calculate the exception ratio. Then, the feature whose associated exception ratio is the minimum is deleted permanently. They iterate this procedure while the exception ratio or its increase is within a specified value by feature deletion. The simulation results show that the current method is better than the principal component analysis (PCA) and performs better than the previous method, especially when the distributions of class data are not parallel to the feature axes     

Monolithic rat-race mixers for millimeter waves

In this paper, we report on fully monolithic millimeter-wave Schottky-barrier diode (SBD) down-converters with an IF amplifier using heterojunction bipolar transistors (HBT's). A rat-race circuit is used for the mixer, and is analyzed using a harmonic-balance simulator. The measured conversion gain and the isolation are 7.1 and 29 dB in the V-band design, and 8.0 and 25 dB in the W-band design, respectively. The conversion gains are matched well with the circuit simulation     

A monolithic DC temperature compensation bias scheme for multistageHEMT integrated circuits

This work benchmarks the first demonstration of a multistage monolithic HEMT IC design which incorporates a DC temperature compensated current-mirror bias scheme. This is believed to be the first demonstrated monolithic HEMT bias scheme of its kind. The active bias approach has been applied to a 2-18 GHz five-section low noise HEMT distributed amplifier which achieves a nominal gain of 12.5 dB and a noise figure <2.5 dB across a 2-18 GHz band, The regulated current-mirror scheme achieves better than 0.2% current regulation over a 0-125°C temperature range, The RF gain response was also measured over the same temperature range and showed less than 0.75 dB gain degradation. This results in a -0.006 dB/°C temperature coefficient which is strictly due to HEMT device G_m variation with temperature. The regulated current-mirror circuit can be employed as a stand-alone V_gs-voltage reference circuit which fan be monolithically applied to the gate bias terminal of existing HEMT ICs for providing temperature compensated performance, This monolithic bias approach provides a practical solution to DC bias regulation and temperature compensation for HEMT MMICs which can improve the performance, reliability, and cost of integrated microwave assemblies (IMAs) used in space-flight military applications