Aggregate input-output models of neuronal populations

An extraordinary amount of electrophysiological data has been collected from various brain nuclei to help us understand how neural activity in one region influences another region. In this paper, we exploit the point process modeling (PPM) framework and describe a method for constructing aggregate input-output (IO) stochastic models that predict spiking activity of a population of neurons in the "output" region as a function of the spiking activity of a population of neurons in the "input" region. We first build PPMs of each output neuron as a function of all input neurons, and then cluster the output neurons using the model parameters. Output neurons that lie within the same cluster have the same functional dependence on the input neurons. We first applied our method to simulated data, and successfully uncovered the predetermined relationship between the two regions. We then applied our method to experimental data to understand the input-output relationship between motor cortical neurons and 1) somatosensory and 2) premotor cortical neurons during a behavioral task. Our aggregate IO models highlighted interesting physiological dependences including relative effects of inhibition/excitation from input neurons and extrinsic factors on output neurons.     

EEFFL: energy efficient data forwarding for forest fire detection using localization technique in wireless sensor network

Wireless Networks - Early prediction of a forest fire is one of the critical research challenges of the wireless sensor network (WSN) to save our ecosystem. In WSN based forest fire detection...     

Temperature dependent drain current model for Gate Stack Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for wide operating temperature range

This paper presents two dimensional temperature dependent analytical model of Gate Stack Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET and compares it with the simulated data using ATLAS 3D device simulator for wide operating temperature i.e. 300–500 K for channel length down to 32 nm technology node. In this work, a temperature dependent analytical expression of drain current for sub-threshold region to saturation region has been developed. Lower sub-threshold slope and reduced leakage current in case of ISESON MOSFET (as compared to ISE and SON) results in better NMOS inverter performance and hence ISESON can be widely used in CCD camera as well as for fast switching applications. Further, we have also investigated the impact of temperature on electrical characteristics of ISESON MOSFET which are important for analog applications.     

Design of reliable universal QCA logic in the presence of cell deposition defect

The emergence of Quantum-dot Cellular Automata (QCA) has resulted in being identified as a promising alternative to the currently prevailing techniques of very large scale integration. QCA can provide low-power nanocircuit with high device density. Keeping aside the profound acceptance of QCA, the challenge that it is facing can be quoted as susceptibility to high error rate. The work produced in this article aims towards the design of a reliable universal logic gate (r-ULG) in QCA (r-ULG along with the single clock zone and r-ULG-II along with multiple clock zones). The design would include hybrid orientation of cells that would realise majority and minority, functions and high fault tolerance simultaneously. The characterisation of the defective behaviour of r-ULGs under different kinds of cell deposition defects is investigated. The outcomes of the investigation provide an indication that the proposed r-ULG provides a fault tolerance of 75% under single clock zone and a fault tolerance of 100% under dual clock zones. The high functional aspects of r-ULGs in the implementation of different logic functions successfully under cell deposition defects are affirmed by the experimental results. The high-level logic around the multiplexer is synthesised, which helps to extend the design capability to the higher-level circuit synthesis.     

Quantum mechanical analytical modeling of nanoscale DG FinFET: evaluation of potential,threshold voltage and source/drain resistance

Two-dimensional (2D) quantum mechanical analytical modeling has been presented in order to evaluate the 2D potential profile within the active area of FinFET structure. Various potential profiles such as surface, back to front gate and source to drain potential have been presented in order to appreciate the usefulness of the device for circuit simulation purposes. As we move from source end of the gate to the drain end of the gate, there is substantial increase in the potential at any point in the channel. This is attributed to the increased value of longitudinal electric field at the drain end on application of a drain to source voltage. Further, in this paper, the detailed study of threshold voltage and its variation with the process parameters are presented. A threshold voltage roll-off with fin thickness is observed for both theoretical and experimental results. The fin thickness is varied from 10 nm to 60 nm. The percentage roll-off for our model is 77% and that for experimental result it is 75%. Form the analysis of source/drain (S/D) resistance, it is observed that for a fixed fin width, as the channel length increases, there is an enhancement in the parasitic S/D resistance. This can be inferred from the fact that as the channel length decreases, quantum confinement along the S/D direction becomes more extensive. For our proposed devices a close match is obtained with the results through the analytical model and reported experimental results, thereby validating our proposed QM analytical model for DG FinFET device.     

Low Voltage High Output Impedance Bulk-Driven Quasi-Floating Gate Self-Biased High-Swing Cascode Current Mirror

A low voltage self-biased high-swing cascode current mirror using bulk-driven quasi-floating gate MOSFET is proposed in this paper. The proposed current mirror bandwidth and especially the output impedance show a significant improvement compared to prior arts. The current mirror presented is designed using bulk-driven and bulk-driven quasi-floating gate N-channel MOS transistors, which helped it to operate at very low supply voltage of \({\pm }0.2\,\hbox {V}\). To achieve high output resistance, the current mirror uses regulated cascode stage followed by super cascode architecture. The small-signal analysis carried out proves the improvement achieved by proposed current mirror. The current mirror circuit operates well for input current ranging from 0 to \(250\,{\upmu }\mathrm{A}\) with good linearity and shows the bandwidth of 285 MHz. The input and output resistances are found as \(240\,\Omega \) and \(19.5\,\hbox {G}\Omega \), respectively. Further, the THD analysis and Monte Carlo simulations carried prove the robustness of proposed current mirror. The complete analysis is done using HSpice on UMC \(0.18\,\upmu \mathrm{m}\) technology.     

Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET

We investigate the performance of an 18 nm gate length AlInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al_0.83In_0.17N and narrowband GaN layers, along with high-k Al₂O₃ as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering (DIBL), subthreshold slope (SS), delay, threshold voltage (V_t), I_on/I_off ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, I_on, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize the I_off and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.     

Crosstalk suppression in networked resistive sensor arrays using virtual ground technique

In 2D resistive sensor arrays, the interconnections are reduced considerably by sharing rows and columns among various sensor elements in such a way that one end of each sensor is connected to a row node and other end connected to a column node. This scheme results in total N?+?M interconnections for N?×?M array of sensors. Thus, it simplifies the interconnect complexity but suffers from the crosstalk problem among its elements. We experimentally demonstrate that this problem can be overcome by putting all the row nodes at virtually equal potential using virtual ground of high gain operational amplifiers in negative feedback. Although it requires large number of opamps, it solves the crosstalk problem to a large extent. Additionally, we get the response of all the sensors lying in a column simultaneously, resulting in a faster scanning capability. By performing lock-in-amplifier based measurements on a light dependent resistor at a randomly selected location in a 4?×?4 array of otherwise fixed valued resistors, we have shown that the technique can provide 86?dB crosstalk suppression even with a simple opamp. Finally, we demonstrate the circuit implementation of this technique for a 16?×?16 imaging array of light dependent resistors.     

Clustering‐based resource discovery on Internet‐of‐Things

Resource discovery on Internet‐of‐Things paradigm is an eminent challenge due to data‐specific activities with respect to foraging and sense‐making loops. The prerequisite to deal with the challenge is to process and analyze the data that require resources to be indexed, ranked, and stored in an efficient manner. A novel clustering technique is proposed to resolve the specified challenge. The technique, namely, iterative k‐means clustering algorithm, targets concrete cluster formation using similarity coefficients of vector space model and performs efficient search against matching criteria with respect to complexity. It is simulated on MATLAB, and the obtained results are compared with fuzzy k‐means and fuzzy c‐means clustering algorithm with similarity coefficients of vector space model against exponential increase in the number of resources.     

Revamping SiO2 Spheres by Core–Shell Porosity Endowment to Construct a Mazelike Nanoreactor for Enhanced Catalysis in CO2 Hydrogenation to Methanol

Beyond the catalytic activity of nanocatalysts, the support with architectural design and explicit boundary could also promote the overall performance through improving the diffusion process, highlighting additional support for the morphology-dependent activity. To delineate this, herein, a novel mazelike-reactor framework, namely multi-voids mesoporous silica sphere (MVmSiO₂), is carved through a top-down approach by endowing core-shell porosity premade Stöber SiO₂ spheres. The precisely-engineered MVmSiO₂ with peripheral one-dimensional pores in the shell and interconnecting compartmented voids in the core region is simulated to prove combined hierarchical and structural superiority over its analogous counterparts. Supported with CuZn-based alloys, mazelike MVmSiO₂ nanoreactor experimentally demonstrated its expected workability in model gas-phase CO₂ hydrogenation reaction where enhanced CO₂ activity, good methanol yield, and more importantly, a prolonged stable performance are realized. While tuning the nanoreactor composition besides morphology optimization could further increase the catalytic performance, it is accentuated that the morphological architecture of support further boosts the reaction performance apart from comprehensive compositional optimization. In addition to the found morphological restraints and size-confinement effects imposed by MVmSiO₂, active sites of catalysts are also investigated by exploring the size difference of the confined CuZn alloy nanoparticles in CO₂ hydrogenation employing both in-situ experimental characterizations and density functional theory calculations.