Resilient Fixed-Order Distributed Dynamic Output Feedback Load Frequency Control Design for Interconnected Multi-Area Power Systems

The paper proposes a novel \begin{document}$ H_\infty$\end{document} load frequency control (LFC) design method for multi-area power systems based on an integral-based non-fragile distributed fixed-order dynamic output feedback (DOF) tracking-regulator control scheme. To this end, we consider a nonlinear interconnected model for multi-area power systems which also include uncertainties and time-varying communication delays. The design procedure is formulated using semi-definite programming and linear matrix inequality (LMI) method. The solution of the proposed LMIs returns necessary parameters for the tracking controllers such that the impact of model uncertainty and load disturbances are minimized. The proposed controllers are capable of receiving all or part of subsystems information, whereas the outputs of each controller are local. These controllers are designed such that the resilient stability of the overall closed-loop system is guaranteed. Simulation results are provided to verify the effectiveness of the proposed scheme. Simulation results quantify that the distributed (and decentralized) controlled system behaves well in presence of large parameter perturbations and random disturbances on the power system.     

A low-power, second-order Δ/Σ modulator using a single class-AB op-amp for voice-band applications

The design of a power-efficient second-order Δ/Σ modulator for voice-band is presented. At system level, a new single-loop, single-stage modulator is proposed. The modulator employs only one class-AB op-amp to realize a second-order noise shaping for voice-band applications. The modulator is designed in a 0.25μm standard CMOS process, and exhibits 86 dB dynamic range (DR) for a 4 kHz voice-bandwidth. The proposed modulator consumes 125μW from a 2.5 V supply. Aminghasem Safarian received the B.S. and M.S. degrees in electrical engineering from the Sharif University of Technology, in 2000, 2002, respectively. Since 2003 he is a research assistant at University of California, Irvine, working toward his Ph.D. degree in electrical engineering emphasizing on RF IC design for wireless communication systems. During the summer of 2005, he was with Broadcom Corporation, Irvine, CA, where he developed integrated receivers for RFID and WCDMA applications. Farzad Sahandiesfanjani was born in Tabriz, Iran in 1976. He received the B.S. and M.S. degrees in electronics from Sharif University of Technology, Tehran, Iran, in 1998 and 2000, respectively. The subject of his thesis was the design of 4th order cascade delta-sigma modulator for ADSL Analog Front End. From 1998 to 2003, he was with Emad Semicon Co., Tehran, Iran, where he designed circuits for voice application such as CODEC and SLIC chip. He also designed a 3rd order single loop class-D delta-sigma modulator for audio application. He joined Tripath Technology Inc., San Jose, CA, in 2003 and has been working on the design of analog and mixed-signal circuits for class-T audio power amplifier. He is also author of one patent for inductor-less switching audio power amplifier and also co-author of 3 more pending patents and 4 papers. Payam Heydari (S'98–M'00) received the B.S. and M.S. degrees (with honors) in electrical engineering from the Sharif University of Technology, in 1992, 1995, respectively. He received the Ph.D. degree in electrical engineering from the University of Southern California, in 2001. During the summer of 1997, he was with Bell-Labs, Lucent Technologies, Murray Hill, NJ, where he worked on noise analysis in deep submicron very large-scale integrated (VLSI) circuits. During the summer of 1998, he was with IBM T. J. Watson Research Center, Yorktown Heights, NY, where he worked on gradient-based optimization and sensitivity analysis of custom-integrated circuits. Since August 2001, he has been an Assistant Professor of Electrical Engineering at the University of California, Irvine, where his research interest is the design of high-speed analog, radio-frequency (RF), and mixed-signal integrated circuits. Dr. Heydari has received the 2005 National Science Foundation (NSF) CAREER Award, the 2005 IEEE Circuits and Systems Society Darlington Award, the 2005 Henry Samueli School of Engineering Teaching Excellence Award, the Best Paper Award at the 2000 IEEE International Conference on Computer Design (ICCD), the 2000 Honorable Award from the Department of EE-Systems at the University of Southern California, and the 2001 Technical Excellence Award in the area of Electrical Engineering from the Association of Professors and Scholars of Iranian Heritage (APSIH). He was recognized as the 2004 Outstanding Faculty at the EECS Department of the University of California, Irvine. His name was included in the 2006 Who's Who in America. Dr. Heydari is an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—part I. He currently serves on the Technical Program Committees of Custom Integrated Circuits Conference (CICC), International Symposium on Low-Power Electronics and Design (ISLPED), International Symposium on Quality Electronic Design (ISQED), and the Local Arrangement Chair of the ISLPED conference. He was the Student Design Contest Judge for the DAC/ISSCC Design Contest Award in 2003, the Technical Program Committee member of the IEEE Design and Test in Europe (DATE) from 2003 to 2004, and International Symposium on Physical Design (ISPD) in 2003. Mojtaba Atarodi received his Ph.D degree from USC (the University of Southern California, Los Angeles), in electrical engineering Electro-physics in 1993, his M.S from University of California at Irvine, and his B.SEE from the Tehran Polytechnic University with first Grade honor. Following his Ph.D completion, he was with Linear Technology Corporation from 1993 to 1996 as an analog design engineer. He has been with Sharif University of Technology as an Assistant and Visiting Professor since 1997. The Author of more than 50 technical journal and conference papers an a book on Analog CMOS IC Design, Dr Atarodi’s main research interests are analog and RF IC system, circuit, and signal processing design as well as analog synthesis tools. Having held several management and consulting positions during the last 15 years in the US industry, he holds one US patent in analog highly linear tunable Operational Transconductance Amplifiers and has applied for 5 more US patents as well.     

Effect of fatty amine and perfluorocarbon as anti‐fouling agent on the catalyst activity and titanium oxidation state in slurry polymerization of ethylene

In this work, the effect of two antifouling materials on the activity of catalyst used to produce polyethylene in a 1‐L slurry reactor and on the titanium oxidation state of the catalyst was investigated. Armostat 300 with the formula alkyl C₁₄‐C₁₈ bis(2‐hydroxyethyl)amine is an antistatic agent that reduces static electricity of the polymer particles. It was found that within the concentration of 0.16–1.32 g/mmol Ti, Armostat 300 helps to increase the catalyst activity to 1.3–2 times. The variation of the titanium oxidation state of the catalyst in the presence of Armostat 300 at 80°C with Al/Ti molar ratio of 100 showed that Ti (III) species increased. The effect of Armostat 300 on T_m, % X_c, density, bulk density, and MFI of polymer was insignificant. In this work, Zonyl FSN‐100 with the formula R_f(CH₂CH₂O)_xH, R_f = F(CF₂CF₂)_y, y = 1–9, x = 1–26 was used as antifouling agent in copolymerization of ethylene with 1‐butene. It was found that Zonyl FSN‐100 at the concentration range of 5–20 ppm reduces the catalyst activity to 1.11–1.9 times. It was also shown that Ti (III) species in the presence of Zonyl FSN 100 decreased. This antifouling agent slightly decreased the properties of polymer including % X_c, density, and M_w. © 2006 Wiley Periodicals, Inc. J Appl Polym Sci 102: 257–260, 2006     

Analysis of catalyst particle strength by impact testing: The effect of manufacturing process parameters on the particle strength

The mechanical strength of porous alumina catalyst carrier beads, used in the reforming units with continuous catalytic regeneration, was measured by impact testing. With this testing method particle strength can be measured at higher strain rates than the traditional crushing test method, hence providing a better simulation of pneumatic conveying and chute flow conditions, and also a large number of particles can be tested quickly. This is important for particles with a brittle failure mode such as the alumina particles used in this work as a wide distribution of mechanical strength usually prevails. Extensive impact testing was carried out first with an industrial sample, in order to understand the failure mechanism of this type of particles and to develop a methodology for analysing the extent of breakage by impact. Then the method was used to analyse the effect of a number of process parameters, such as filler, macroporosity and drying procedure on the particle strength with the aim of optimising the manufacturing process. The impact test results were then used to test the model of breakage behaviour of particulate solids proposed by Vogel and Peukert [Vogel and Peukert, Breakage behaviour of different materials—construction of a mastercurve for the breakage probability. Powder Technol., 129 (2003) pp. 101-110].     

A Wide Tuning Range, Fractional Multiplying Delay-Locked Loop Topology for Frequency Hopping Applications

This paper introduces a low-jitter and wide tuning range delay-locked loop (DLL) -based fractional clock generator (CG) topology. The proposed fractional multiplying DLL (FMDLL) architecture overcomes some disadvantages of phase-locked loops (PLLs) such as jitter accumulation while maintaining the advantageous of a PLL as a multi-rate fractional frequency multiplier. Based on this topology, a CG with 1–2.5 GHz output frequency tuning range has been designed in a digital 0.18 um CMOS technology while the multiplication ratios are M+k/(2N_C) in which M, k, and N_C are adjustable. To generate some finer ratios, k is changed periodically or randomly (by a digital delta-sigma modulator) between two consecutive integer numbers. Operating in 2.5 GHz, total circuit including digital part consumes 15.5 mW from 1.8 V supply voltage. At the proposed architecture, reference clock is injected into a ring oscillator in specified times and to the specified delay-stages to synthesize the fractional frequency multiplication as well as resetting the accumulated jitter during previous cycles. Operating in maximum speed, simulated RMS (root-mean-square) and PTP (peak-to-peak) jitter values are 1.8 and 14.5 ps, respectively, while the settling time is 5 us. Armin Tajalli received the B.Sc. from Sharif University of Technology (SUT), Tehran, Iran, in 1997, and M.Sc. from Tehran Polytechnic University, Tehran, Iran, in 1999. From 1998 he has joint Emad Co. as a senior design engineer where he has worked on several industrial and R&D projects on analog and mixed-mode ICs. He received the award of the Best Design Engineer from Emad Co., 2001, the Kharazmi Award of Industrial Research and Development, Iran, 2002, and Presidential Award of the Best Iranian Researchers, in 2003. He is now working toward his Ph.D. degree at SUT. His current interests are design of high speed circuits for telecommunication systems. Pooya Torkzadeh was born in Isfahan, on April 21, 1980. He received the B.Sc. degree from Isfahan University of Technology (IUT), Isfahan, in 2002 and the M.Sc. degree from Sharif University of Technology (SUT), Tehran, in 2004, both in electrical engineering. From 2002 to 2004, he was an Assistant with SUT and the member of Sharif Integrated Circuit And System Group (SICAS). His major activities are in Electronics Integrated Circuit Designing and Digital Signal Processing (DSP). He specializes in CMOS Integrated Circuits particularly for Clock Generation, Clock-Data Recovery Systems, and Sigma-Delta Analogue to Digital Converter Applications. Mojtaba Atarodi received the B.S.E.E. from Amir Kabir University of Technology (Tehran Polytechnic) in 1985, and M.Sc. degree in electrical engineering from the University of California, Irvine, in 1987. He received the Ph.D. degree from the University of Southern California (USC) on the subject of analog IC design in 1993. From 1993 to 1996 he worked with Linear Technology Corporation as a senior analog design engineer. Since then, he has been consulting with different IC companies. He is currently a visiting professor at Sharif University of Technology. He has published more than 30 technical papers in the area of analog and mixed-signal integrated circuit design as well as analog CAD tools.     

Critical Influence of Mn on Low-Temperature Catalytic Activity of Mn/Na2WO4/SiO2 Catalyst for Oxidative Coupling of Methane

Oxidative coupling of methane (OCM) was investigated in the temperature range 370-775 °C over Mn/Na₂WO₄/SiO₂ catalysts with different loadings of manganese in integral-mode conditions. Na₂WO₄/SiO₂ shows no activity at low temperature (370 °C), whereas Mn-doped catalyst exhibits 14% C²⁺ yield under similar reaction conditions, indicating that manganese plays a critical role in low-temperature methane coupling reaction. Partial pressure of oxygen in the feed also influences the low-temperature OCM activity of the catalysts.     

Lithium diffusion profile onto highly resistive p-type silicon

In this work, the effect of temperature and time of diffusion on the lithium (Li) profile into p-type highly resistive silicon have been investigated. The high-purity Li metal (99.995%) was deposited onto p-type (1 1 1) silicon surface and thermally diffused into the bulk at a 2×10⁻⁶ Torr vacuum pressure. The four-probes technique was used to determine the diffusion profile of Li impurities into silicon. Scanning electron microscopy (SEM) was used to measure the diffused junction depth (X_j). The Li diffusion constant D_Li was then extracted using the measured surface concentration N_Li. Thus, the variation of D_Li as a function of diffusion temperature was determined. Simulated profiles was obtained by means PC1D calculate tool. A good agreement was found when the simulated and experimental results were compared with those of the literature values.     

Triaxial shear behavior of a cement-treated sand——gravel mixture

A number of parameters,e.g.cement content,cement type,relative density,and grain size distribution,can influence the mechanical behaviors of cemented soils.In the present study,a series of conventional triaxial compression tests were conducted on a cemented poorly graded sandegravel mixture containing 30% gravel and 70% sand in both consolidated drained and undrained conditions.Portland cement used as the cementing agent was added to the soil at 0%,1%,2%,and 3%(dry weight) of sandegravel mixture.Samples were prepared at 70% relative density and tested at confining pressures of 50 kPa,100 kPa,and150 kPa.Comparison of the results with other studies on well graded gravely sands indicated more dilation or negative pore pressure in poorly graded samples.Undrained failure envelopes determined using zero Skempton's pore pressure coefficient (= 0) criterion were consistent with the drained ones.Energy absorption potential was higher in drained condition than undrained condition,suggesting that more energy was required to induce deformation in cemented soil under drained state.Energy absorption increased with increase in cement content under both drained and undrained conditions.