Isolation and characterization of hardening-induced proteins in Chlorella vulgaris C-27: identification of late embryogenesis abundant proteins

Hardening-induced soluble proteins of Chlorella vulgaris Beijerink IAM C-27 (formerly Chlorella ellipsoidea Gerneck IAM C-27) were isolated and purified by two-dimensional high-performance liquid chromatography (2D-HPLC) on an anion-exchange column, with subsequent reversed-phase chromatography. Some of the proteins were resolved by SDS-PAGE, characterized by amino-terminal sequencing and identified by searching for homologies in databases. Separation of the soluble proteins during the hardening of Chlorella by a combination of 2D-HPLC and SDS-PAGE revealed that at least 31 proteins were induced or increased in abundance. Of particular interest was the induction after 12 h of a 10-kDa protein with the amino-terminal amino acid sequence AGNKPITEQISDAVGAAGQKVG and the induction after 6 h of a 14-kDa protein with the amino-terminal sequence ALGEESLGDKAKNAFEDAKDAVKDAAGNVKEAV. The amino-terminal sequences of these proteins indicated that they were homologous to late embryogenesis abundant (LEA) proteins. Furthermore, the level of a 22-kDa protein also increased after 12 h. The amino-terminal sequence of this protein, AAPLVGGPAPDFTAAAVFD, indicated that it was homologous to thioredoxin peroxidase.     

Subthreshold properties of TFTs with laser-crystallized laterally grown polysilicon layers

Trap-density analysis of laterally grown polysilicon films formed by continuous-wave laser revealed the main factor that controls the subthreshold property of low-temperature polysilicon thin-film transistors. In the low-current region, traps at the gate oxide/polysilicon interface are charged and the consequent insensitiveness of polysilicon surface potential to gate bias dominates the subthreshold property. In the higher current region, that is, close to the threshold voltage, a transport mechanism in which carriers are scattered at the grain boundaries becomes the dominant factor governing the subthreshold property.     

Dielectric strength of transformer insulation at DC polarityreversal

Among special insulation tests for DC power converter transformers, polarity reversal tests can be substituted by applied AC voltage tests from a stress similarity in oil ducts. In order to investigate equivalent levels of other insulation tests to polarity reversal tests, the dielectric strength of a transformer at polarity reversals was examined by use of a model of typical oil/paper composite insulation. From the comparison of polarity reversal and other insulation tests, it was found that dielectric strength of transformer insulation at polarity reversals is phenomenally similar to that under switching impulse stresses. Equivalent AC test voltage to polarity reversal test was also estimated from the experimental results. The breakdown characteristics of polarity reversal tests showed that partial discharges at polarity reversals impose less harmful stress on insulation barriers than those at usual AC or impulse tests     

A 1-inch 2-M pixel HDTV CCD image sensor with tungsten photo-shieldand H-CCD shunt wiring

A 1-inch 2-million pixel FIT-CCD image sensor for HDTV has been developed, which features a tungsten photo-shield and horizontal CCD (H-CCD) shunt wiring. Tungsten photo-shield, which has low reflectance and good step coverage characteristics, reduces smear level to -110 dB, combined with a frame-interline-transfer (FIT) scheme. The tungsten photo-shield also acts as a shunt busline, supplying transfer pulses to vertical CCD (V-CCD) electrodes, so that a 1.2×10ˆ5 electron charge handling capability is obtained at a frame transfer frequency of 1 MHz. Newly developed H-CCD shunt wiring suppresses vertical line pair FPN, even with smaller transfer pulse amplitudes. H-CCD shunt wiring also helps reduce power consumption in the H-CCD by 2/3 as compared to that achieved with conventional wiring     

An all DC-powered Josephson logic circuit

A novel DC-powered Josephson circuit is reported. An improved HUFFLE-type DC flip-flop with a parallel resistor, to prevent hang-up, is constructed by combinational circuits as well as sequential circuits. The basic device is a vertical type two-junction interferometer with only three-metal layers. The design rule is 2.5 μm. High junction-current density allows for a wide operating margin even with a low inductance load. Basic circuit function test elements have been completed. The DC flip-flop with excess gate current works as a GHz range VCO (voltage controlled oscillator) for internal clock generation. The speedup junction successfully accelerated the switching speed. The ring-oscillator showed a minimum gate delay of 11.3 ps