Power Optimization in VLSI Layout: A Survey

This paper presents a survey of layout techniques for designing low power digital CMOS circuits. It describes the many issues facing designers at the physical level of design abstraction and reviews some of the techniques and tools that have been proposed to overcome these difficulties.     

Variable Power Combiner for RF Mode Shimming in 7-T MR Imaging

This contribution discusses the utilization of RF power in an MRI system with RF mode shimming which enables the superposition of circularly polarized modes of a transmit RF coil array driven by a Butler matrix. Since the required power for the individual modes can vary widely, mode-shimming can result in a significant underutilization of the total available RF power. A variable power combiner (VPC) is proposed to improve the power utilization: it can be realized as a reconfiguration of the MRI transmit system by the inclusion of one additional matrix network which receives the power from all transmit amplifiers at its input ports and provides any desired (combined) power distribution at its output ports by controlling the phase and amplitude of the amplifiers' input signals. The power distribution at the output ports of the VPC is then fed into the "mode" ports of the coil array Butler matrix in order to superimpose the spatial modes at the highest achievable power utilization. The VPC configuration is compared to the standard configuration of the transmit chain of our MRI system with 8 transmit channels and 16 coils. In realistic scenarios, improved power utilization was achieved from 17% to 60% and from 14% to 55% for an elliptical phantom and a region of interest in the abdomen, respectively, and an increase of the power utilization of 1?dB for a region of interest in the upper leg. In general, it is found that the VPC allows significant improvement in power utilization when the shimming solution demands only a few modes to be energized, while the technique can yield loss in power utilization in cases with many modes required at high power level.     

NBTI and hot-carrier effects in accumulation-mode Pi-gate pMOSFETs

Negative bias temperature instability (NBTI) and hot-carrier induced device degradation in accumulation-mode Pi-gate pMOSFETs have been studied for different fin widths ranging from 20 to 40 nm. The NBTI induced device degradation is more significant in narrow devices. This result can be explained by enhanced diffusion of hydrogen at the corners in multiple-gate devices. Due to larger impact ionization, hot-carrier induced device degradation is more significant in wider devices. Finally, hot-carrier induced device degradation rate is highest under stress conditions where V_GS = V_TH.     

Frequency domain damage detection of plate and shell structures by finite element model updating

Plate- and shell-like elements are the main constituent of many engineering structures such as ships and airplanes. This paper develops a frequency domain model updating method using power spectral density function and seeks its viability in damage identification of plates and shells. The derivation of the sensitivity equation is exact and measured natural frequencies of few lower modes are used to overcome the drawbacks of incomplete measurement. The method is numerically examined in several damage cases. The robustness of method against measurement and mass modelling error is numerically assessed using Monte-Carlo analysis and numerically simulated error contaminated data. The method proves to be robust against both kind of errors and performs well, both in cases of plate and shell elements.     

Low power DCVSL circuits employing AC power supply

In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design, which adopts a gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals. Then the design procedure is summed up for converting complementary CMOS logic gates employing DC power to the power-clocked CMOS gates employing AC power. On this basis, the design of differential cas-code voltage switch logic (DCVSL) circuits employing AC power clocks is proposed. The PSPICE simulations using a sinusoidal power-clock demonstrate that the designed power-clocked DCVSL circuit has a correct logic function and low power characteristics. Finally, an interface circuit to convert clocked signals into the standard logic levels of a CMOS circuit is proposed, and its validity is verified by computer simulations.     

Two high-performance and low-power serial communication interfaces for on-chip interconnects

This paper presents two novel methods for on-chip serial communication in which the clocks of the transmitter and the receiver are generated with two separate ring oscillators. These oscillators are identical, although they can have a small frequency difference. In the first method, a strobe line that toggles exactly once with every frame of n-bit data is used to activate the oscillators. Local counters are used to count the number of bits in the data frame and to stop the local oscillators when the frame has been processed. In the second method, a single physical line is used to transmit both data and (in-band) control information, further reducing the power dissipation. The data transmission is controlled by the output of a starter flip-flop that indicates the empty/full state of an input buffer, whereas the data reception is controlled by the decoding of a ?1? start bit and a ?0? end bit, both of which are added to the n-bit data word to form a frame. Circuit simulation results demonstrate that both communication methods have high bandwidth and low power dissipation.