Classification of pixels in a noisy grayscale image of polar ice

Often, in synthetic aperture radar (SAR) images of polar ice, one encounters shadow-like features across the images. Such features make it difficult to classify pixels into ice and water. Accordingly, it becomes a challenge to determine the true size and boundaries of ice floes in an SAR image of polar ice. We develop a simple statistical procedure which classifies pixels of an image by eliminating the effects of shadow-like features. Methodology developed in this paper is illustrated using some noisy SAR images of ice floes in the Arctic sea.     

A new MMIC broadside coupler using an array of air-bridges for directivity enhancement

A new quadrature broadside coupler is proposed, which employs an array of air-bridges to enhance directivity via its phase-equalization effect on the c-mode and /spl pi/-modes. The realization of air-bridges follows a standard MMIC fabrication process. An experimental chip fabricated on the 75-/spl mu/m GaAs substrate verifies the air-bridge effect and shows wideband characteristics of the coupling of 3.2/spl plusmn/0.4 dB, the insertion loss of 3.9/spl plusmn/0.4 dB, the output phase deviation from quadrature less than 6/spl deg/, and the isolation greater than 18 dB from 20 to 40 GHz.     

Test data compression and test time reduction using an embedded microprocessor

Systems-on-a-chip (SOCs) with many complex intellectual property cores require a large volume of data for manufacturing test. The computing power of the embedded processor in a SOC can be used to test the cores within the chip boundary, reducing the test time and memory requirements. This paper discusses techniques that use the computing power of the embedded processor in a more sophisticated way. The processor can generate and reuse random numbers to construct test patterns and selectively apply only those patterns that contribute to the fault coverage, significantly reducing the pattern generation time, the total number of test applications and, hence, the test time. It can also apply deterministic test patterns that have been compressed using the characteristics of the random patterns as well as those of the deterministic patterns themselves, which leads to high compression of test data. We compare three fast run-length coding schemes which are easily implemented and effective for test-data compression. We also demonstrate the effectiveness of the proposed approach by applying it to some benchmark circuits and by comparing it with other available techniques.     

A One‐Kilobit PQR‐CMOS Smart Pixel Array

The photonic quantum ring (PQR) laser is a three dimensional whispering gallery (WG) mode laser and has anomalous quantum wire properties, such as microampere to nanoampere range threshold currents and √T‐dependent thermal red shifts. We observed uniform bottom emissions from a 1‐kb smart pixel chip of a 32×32 InGaAs PQR laser array flip‐chip bonded to a 0.35 µm CMOS‐based PQR laser driver. The PQR‐CMOS smart pixel array, now operating at 30 MHz, will be improved to the GHz frequency range through device and circuit optimization.     

A graphic approach to performance analysis of multistage linear interference canceller in long-code CDMA systems

The signal-to-interference-plus-noise-ratio performance of the multistage linear parallel and successive interference cancellers (LPIC and LSIC) in a long-code code-division multiple-access system is analyzed using a graphical approach. The decision statistic is modeled as a Gaussian random variable, whose mean and variance can be expressed as functions of moments of R for the LPIC and L for the LSIC, respectively, where R is the correlation matrix of signature sequences and L is the strict lower triangular part of R. Since the complexity of calculating these moments increases rapidly with the growth of the stage index, a graphical representation of moments is developed to facilitate the computation. Propositions are presented to relate the moment calculation problem to several well-known problems in graph theory, i.e., the coloring, the graph decomposition, the biconnected component finding, and the Euler tour problems. It is shown that the derived analytic results match well with simulation results.     

Extraction of penicillin G from simulated media by an emulsion liquid membrane process

The extraction of penicillin G from simulated media was performed by water/oil/water (w/o/w) emulsion liquid membranes (ELMs) and studied under various operational conditions in a batch system. The degree of extraction achieved was between 80% and 95% under specific conditions. A concentration of greater than nine times the initial concentration of penicillin G in the external phase was obtained in the internal phase. The pH of the internal aqueous solution, containing a basic salt, was theoretically calculated on the basis of the amount of penicillin G transported into the internal phase. The calculated results agreed with the experimental data well and were used to select a suitable type and concentration of a basic salt in the internal phase to give a pH within the range 5 to 8 where penicillin G was stable after the termination of extraction. The extraction of penicillin G was successfully performed by the ELM process with sodium carbonate in the internal phase.     

Monolithic SiGe Up‐/Down‐Conversion Mixers with Active Baluns

The purpose of this paper is to describe the implementation of monolithically matching circuits, interface circuits, and RF core circuits to the same substrate. We designed and fabricated on‐chip 1 to 6 GHz up‐conversion and 1 to 8 GHz down‐conversion mixers using a 0.8 µm SiGe hetero‐junction bipolar transistor (HBT) process technology. To fabricate a SiGe HBT, we used a reduced pressure chemical vapor deposition (RPCVD) system to grow a base epitaxial layer, and we adopted local oxidation of silicon (LOCOS) isolation to separate the device terminals. An up‐conversion mixer was implemented on‐chip using an intermediate frequency (IF) matching circuit, local oscillator (LO)/radio frequency (RF) wideband matching circuits, LO/IF input balun circuits, and an RF output balun circuit. The measured results of the fabricated up‐conversion mixer show a positive power conversion gain from 1 to 6 GHz and a bandwidth of about 4.5 GHz. Also, the down‐conversion mixer was implemented on‐chip using LO/RF wideband matching circuits, LO/RF input balun circuits, and an IF output balun circuit. The measured results of the fabricated down‐conversion mixer show a positive power conversion gain from 1 to 8 GHz and a bandwidth of about 4.5 GHz.     

Shortest path algorithms: A computational study with the C programming language

The main purpose of this study is to evaluate the computational efficiency of algorithms for calculating shortest paths when they are correctly coded by using the C programming language. The eight algorithms that we selected for this experiment are the most efficient, either measured in terms of worst-case bounds or marked as such from previous computational studies; they include the redistributive heap algorithm. We suggest computer implementations that use the full power of C. In particular, the network representation and the various data structures used to keep the scan eligible list may be managed by using only additions and no multiplications, while it is not possible with FORTRAN. These capabilities, unique to C, yield several interesting conclusions: one may expect to speed up a shortest path algorithm by a factor of 20%; in some cases, this factor may reach 30%. Interestingly, the level of programming difficulty required to achieve these benefits is not greater than that required by implementations using arrays.     

复合材料压缩破坏模式的缺陷敏感性

本文基于弹塑性分叉理论研究单向纤维增强复合材料的压缩破坏模式和压缩强度对缺陷的敏感性问题。对于常见复合材料,所得结论是:无缺陷或者小缺陷情况的破坏模式为倾斜破坏带;大缺陷情况的破坏模式为水平破坏带;形成水平破坏带的压力值小于形成倾斜破坏带的压力。     

Output probability from a general combinational network

In this paper, we present the method which calculates the probability of the output of a general combinational network being 1, when the probabilities is given for each input being 1. Also we present the method which derives the output probability expression in terms of a given set of input probabilities.The method is based on a basic probability axiom and Binary Decision Diagrams. A Boolean function for a combinational network is transformed into a Binary Decision Diagram and the output probability expression is derived from it. Therefore a derivation of the output probability for a combinational network can be straightforward. Some examples are showed that the method using Binary Decision Diagrams is simple and efficient. We can see a variation of the output probability for a combinational network according to the given set of input probabilities.