Mathematical modelling of mass transfer in the concentration polarisation layer of flat‐sheet membranes during clarification of pomegranate juice

Evaluation of membrane clarification of pomegranate juice showed that a cake layer is created at the beginning of the process. This evaluation was used as the basis for modelling the solute concentration in the concentration polarisation layer to control the fouling of the membrane. The model of changes in concentration as a function of time and distance (in its dimensionless form) was solved numerically using the Forward‐Time/Central‐Space (FTCS) method. Programming was performed using MATLAB software, and the predicted concentration on the membrane surface was compared with experimental data; the prediction fit well with the experimental data. The model showed that the solute concentration increased as distance to the membrane surface decreased, time increased, transmembrane pressure increased and velocity decreased. Also, the model matched the experimental data in that it showed the cake layer to be created in the early stages of the membrane clarification process.     

Synthesis of novel dyestuffs containing sulphonamido moieties and their application on wool and polyamide fibres

A new series of azo disperse dyestuffs were prepared by the reaction of sulphanilamidodiazonium chloride derivatives with indan-1,3-dione. Application of these dyes on wool and nylon 6.6 gave excellent results. The synthesised compounds show good biological activity towards different microorganisms.     

Ability of adaptive filters to track carrier offsets and channelnonstationarities

This paper studies the tracking performance of adaptive filters operating in the presence of two sources of nonstationarities: carrier frequency offsets and random channel variations. Both impairments are common in digital communications due to mismatches between transmitter and receiver carrier generators and channel fading. The paper derives expressions for the mean-square error and shows how filter performance is degraded under such nonstationary conditions. Selections of step sizes for optimal tracking performance are derived, different adaptive algorithms are compared, and supporting simulation results are provided     

Investigation of electrical and optical properties of polyvinyl acetate doped with some polymers

Polyglycerol (PG) and polytriethanolamine(PTEA) have been prepared. The electrical resistivity (ρ) and the optical absorption of polyvinylacetate (PVAc) doped with polyglycerol (PG), polyaniline (PA), and polytriethanolamine (PTEA) have been studied. It was found that the conduction was mainly ionic in the temperature range from 20 to 120°C. The resistivity decreased with the increase of the dopant cocentration. The optical absorption spectra were determined in the wavelength range 400–2500 nm. The analysis of the absorption spectra showed that the intensity of the bands is remarkably affected by the dopant concentration. The optical energy gap of pure PVAc and the samples containing different dopants were estimated. © 2002 Wiley Periodicals, Inc. J Appl Polym Sci 86: 1558–1563, 2002     

Extending and Enhancing the Properties of Porous Cordierite Ceramics by Mo6+ ion Incorporation via Facile Combined Synthesis Technique

Molybdenum‐doped cordierite ceramics have been fabricated through facile combined techniques, coprecipitation followed by solid state. XRD results revealed that α‐cordierite phase is predominated with increasing Mo⁶⁺ ion content. The density measurements showed that the bulk density reduced to the minimum value of 0.61 g/cm³, which corresponds to the maximum porosity of about 76.8% at 5% Mo⁶⁺ ion. The dielectric permittivity (ε) of pure cordierite is decreased with increasing Mo⁶⁺ ion content. The minimum dielectric loss of Mo‐doped cordierite at 1 MHz was equal 0.008 with 10% Mo⁶⁺, while at 1 GHz was equal 0.03 with 5% Mo⁶⁺.     

Energy efficient and robust allocation of interdependent tasks on mobile ad hoc computational grid

A mobile ad hoc computational grid is a distributed computing infrastructure that allows mobile nodes to share computing resources in a mobile ad hoc environment. Compared to traditional distributed systems such as grids and clouds, resource allocation in mobile ad hoc computational grids is not straightforward because of node mobility, limited battery power and an infrastructure‐less network environment. The existing schemes are either based on a decentralized architecture that results in poor allocation decisions or assume independent tasks. This paper presents a scheme that allocates interdependent tasks and aims to reduce task completion time and the amount of energy consumed in transmission of data. This scheme comprises two key algorithms: resource selection and resource allocation. The resource selection algorithm is designed to select nodes that remain connected for a longer period, whereas the resource assignment or allocation algorithm is developed to allocate interdependent tasks to the nodes that are accessible at the minimum transmission power. The scheme is based on a hybrid architecture that results in effective allocation decisions, reduces the communication cost associated with the exchange of control information, and distributes the processing burden among the nodes. The paper also investigates the relationship between the data transfer time and transmission energy consumption and presents a power‐based routing protocol to reduce data transfer costs and transmission energy consumption. Copyright © 2014 John Wiley & Sons, Ltd.     

Analysis of Acceleration Effect in Data Dissemination in Vehicular Networks Using Rateless Codes

Mobility models of nodes have an important role in the evaluation of data dissemination protocols in vehicular ad hoc networks (VANETs). Many recent researches have used the constant velocity mobility models while vehicles have acceleration and their speeds change as they move. Because of the dynamic nature of VANETs, the network changes from a densely connected to the sparsely connected environment in a short time. In sparsely connected networks, it is said that vehicles move in clusters. In this paper, the constant acceleration mobility calculations for the sparsely connected network and its characteristics have been presented. These characteristics are usable for the evaluation of the data dissemination protocols in VANETs. The results show that acceleration affects the number of viewed clusters during the trip and the number of vehicles within a cluster. In fact, acceleration has a significant impact on the network sparsely connection. This matter shows that the appropriate data dissemination protocol should be used to study the acceleration effect which is applicable in sparse networks. The analysis in this research provides the necessary background for better understanding and accurate calculations for the evaluation of data dissemination in VANETs.     

FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm

This paper presents a high throughput digital design of the 128-bit Advanced Encryption Standard (AES) algorithm based on the 2-slow retiming technique on FPGA. The C-slow retiming is a well-known optimization and high performance technique. It can enhance designs with feedback loops and automatically rebalances the registers in the design. The C-slow retiming can break the critical path of the design into finer pieces to improve the throughput of the design. The complexity of the C-slow retiming on FPGA is to find the best register allocation in the data path of the design so that by increasing the number of registers, relocation of the registers to balance the AES architecture be in the best mode, and the critical path be optimally pipelined and improved. In this paper, architecture of the AES algorithm is implemented in the gate level by high-speed and breakable structures that are desirable for the 2-slow retiming. The Mix-columns transformation is implemented based on multiplication by constants 2 and 3 modules with combinational logic circuits. This work has been successfully verified and synthesized using Xilinx ISE 11 byVirtex-5, XC5VLX85 FPGA. The proposed implementation achieves a high throughput of 86 Gb/s and high maximum operation frequency of 671.524 MHz whereas the highest throughput and the highest operation frequency reported in the literature are 73.737 Gb/s and 576.07 MHz, respectively.