Effects of PAI on interface properties between HfSiO gate dielectric and silicon substrate

The effects of preamorphization implantation (PAI) on the interface properties between hafnium-silicate (HfSiO) gate dielectrics and silicon substrates were examined. In the case of an NH/sub 3/ nitrided interface, it was found that the PAI can improve the interface trap density (D/sub IT/) compared with the no PAI case. However, for the PAI samples, it was also found that samples with sacrificial screening oxide (Sac Ox) had worse interface properties compared with the samples without Sac Ox. It is attributed to the recoiled oxygen from Sac Ox during PAI.     

Multipath structure for FSR expansion in waveguide-based optical ring resonator

A multipath structure of a ring resonator is proposed to expand the free spectral range. Simulation work indicates that the multipath ring resonator has 25 GHz-adjacent-channel crosstalk of -41 dB, maximum interchannel crosstalk of -18 dB, and -1 dB bandwidth of 4 GHz for a typical expansion factor of 10. The results show the advantages of characteristics compared with a double-cavity ring resonator and a triple-coupler ring resonator.     

An AlxGa1-xSb avalanche photodiode with again bandwidth product of 90 GHz

An Al_xGa_1-xSb avalanche photodiode (APD) with an Al composition of 0.05 has been fabricated and tested. The measured gain-bandwidth (GB) product of the highly doped diode is 90 GHz. Such a large GB product has never been previously achieved by any APD materials sensitive in the long-wavelength region. This suggests the advantage of the Al_xGa_1-xSb material system for very high-speed operation     

Highly reliable copper dual-damascene interconnects with self-formed MnSi/sub x/O/sub y/ barrier Layer

Copper (Cu) dual-damascene interconnects with a self-formed MnSi/sub x/O/sub y/ barrier layer were successfully fabricated. Transmission electron microscopy shows that approximately 2-nm thick and continuous MnSi/sub x/O/sub y/ layer was formed at the interface of Cu and dielectric SiO/sub 2/, and that no barrier was formed at the via bottom because no oxygen was at the via bottom during annealing. No leakage-current increase was observed, and electron energy loss analysis shows that no Cu was in SiO/sub 2/, suggesting that MnSi/sub x/O/sub y/ layer has sufficient barrier properties for Cu, and that the concept of self-forming barrier process works in Cu dual-damascene interconnects. Via chain yield of more than 90% and 50% reduction in via resistance were obtained as compared with physical vapor deposited tantalum barrier, because there is no barrier at the via bottom. In addition, no failure in the stress-induced voiding measurement was found even after a 1600-h testing. No failure in electromigration (EM) testing was found, as the electron flow is from the lower level interconnects through via up to upper level interconnects even after 1000-h testing. At least, four times EM lifetime improvement was obtained in the case of electron flow from upper level interconnect through via down to lower level interconnects. Significant EM lifetime improvement is due to no flux divergence site at the via bottom, resulting from there being no bottom barrier at the via.     

Scalable architecture for word HMM-based speech recognition and VLSI implementation in complete system

This paper describes a scalable architecture for real-time speech recognizers based on word hidden Markov models (HMMs) that provide high recognition accuracy for word recognition tasks. However, the size of their recognition vocabulary is small because its extremely high computational costs cause long processing times. To achieve high-speed operations, we developed a VLSI system that has a scalable architecture. The architecture effectively uses parallel computations on the word HMM structure. It can reduce processing time and/or extend the word vocabulary. To explore the practicality of our architecture, we designed and evaluated a complete system recognizer, including speech analysis and noise robustness parts, on a 0.18-/spl mu/m CMOS standard cell library and field-programmable gate array. In the CMOS standard-cell implementation, the total processing time is 56.9 /spl mu/s/word at an operating frequency of 80 MHz in a single system. The recognizer gives a real-time response using an 800-word vocabulary.     

Quantum flux parametron: a single quantum flux device for Josephsonsupercomputer

A quantum flux parametron (QFP), a single quantum flux superconductive device that has a potential of up to 100-GHz switching with nW-order power dissipation, is considered. The potential of the QFP and key technologies when QFPs are applied to a Josephson supercomputer are described. Switching speed, stability, and power dissipation of a QFP are discussed. QFP gates, circuits, and systems are next described. Then, ultra-fast clock distribution using a standing wave is explained. High-speed operation at more than 10 GHz and 10¹⁴ error-free operations per QFP have been demonstrated. Finally described is a high-density packaging scheme by three-dimensional integration, which is very important for ultra-high speed circuits because the propagation delay becomes dominant in such circuits     

Advances in Digital Front-End and Software RF Processing:Part I

One of the biggest technology trends in wirelessbroadband, radar, sonar, and broadcasting systems issoftware radio frequency processing and digitalfront-end. This trend encompasses a broad range oftopics, from circuit design and signal processing to systemintegration. It includes digital up-conversion (DUC) and     

用电子束曝光方法在优化设计的绝缘体上硅脊状波导上实现布拉格光栅的制作和评价

报道了一种用电子束曝光的方法在绝缘体上硅的脊状光波导上制做布拉格光栅的技术.考虑到实际的光子学集成的应用,讨论了这个带有布拉格光栅的脊状光波导的优化设计,给出了该布拉格光栅的测试和理论模拟结果.通过薄化绝缘体上硅的波导层的厚度和光栅的深腐蚀加工,获得了高达30cm-1的光栅耦合系数.     

Experimental and numerical analysis of channel-length-dependent electrical properties in bottom-gate,bottom-contact organic thin-film transistors with Schottky contact

Channel length dependence of field-effect mobility and source/drain parasitic resistance in pentacene thin-film transistors with a bottom-gate, bottom-contact configuration was investigated. Schottky barrier effect such as nonlinear behaviors in transistor output characteristics appeared and became more prominent for shorter channel length less than 10 μm, raising some concerns for a simple utilization of conventional parameter extraction methods. Therefore the gate-voltage-dependent hole mobility and the source/drain parasitic resistance in the pentacene transistors were evaluated with the aid of device simulation accounting for Schottky contact with a thermionic field emission model. The hole mobility in the channel region shows smaller values with shorter channel length even after removing the influence of Schottky barrier, suggesting that some disordered semiconductor layers with low carrier mobility exist near the contact electrode. This experimental data analysis with the simulation enables us to discuss and understand in detail the operation mechanism of bottom-gate, bottom-contact transistors by considering properly each process of charge carrier injection, carrier flow near the contact region, and actual channel transport.     

An AlGaAs/GaAs short-cavity laser and its monolithic integration using microcleaved facets (MCF) process

This paper describes the microcleaved facets (MCF) process developed for AlGaAs/GaAs laser fabrication which can avoid the previous substrate cleavage and therefore be applicable to preparing both discrete short-cavity lasers and optoelectronic integrated circuits (OEIC's). An AlGaAs/GaAs double heterostructure ridge-waveguide laser with an extremely short cavity length, namely 20 μm, was first realized by this process. A threshold current as low as 20 mA and a single longitudinal mode lasing were achieved. The usefulness of this process for integrating a laser and a monitoring photodiode on a GaAs substrate is also demonstrated.