Alternate Testing of RF Transceivers Using Optimized Test Stimulus for Accurate Prediction of System Specifications

In the recent past, with the emergence of System-on-Chip (SoC), focus has shifted towards testing system specifications rather than device or module specifications. While the problem of test accessibility for test stimulus application and response capture for such high-speed systems remains a challenge to the test engineers, new test strategies are needed which can address the problem in a practical manner. In this paper, the problem of testing the transmitter and the receiver subsystems of a RF transceiver for system level specification is addressed. Instead of using different conventional test stimuli for testing each of the system level specifications of RF subsystems, a specially crafted test stimulus is used for testing all the specifications from the response of the subsystem-under-test. A new simulation approach has also been developed to perform fast behavioral simulations in frequency domain for the system-under-test. In the test method, frequency domain test response spectra are captured and non-linear regression models are constructed to map the spectral measurements onto the specifications of interest. In the presented simulation results, the test stimuli have been validated using netlist level simulation of the subsystem-under-test and specifications have been predicted within an error of ±3% of the actual value.Soumendu Bhattacharya was born in Calcutta, India, in 1978. He received his Bachelors degree from Indian Institute of Technology, Kharagpur, India, in 2000. In 2002, he received the M.S.E.E. degree in electrical engineering from Georgia Institute of Technology, Atlanta, USA. He is currently working toward his Ph.D. degree. In the summer of 2001, he worked as a summer intern in National Semiconductor, Santa Clara, CA, USA. His research interests are in the area of test generation for mixed-signal and RF circuits and systems and design-for-test.Achintya Halder received the B.S. degree in electronics and electrical communication engineering from the Indian Institute of Technology, Kharagpur, in 1998. He worked as an IC design engineer with Texas Instruments until 2000. Currently, he is a Ph.D. student and a research assistant with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta. His research area is analog/RF and mixed signal testing.Ganesh P. Srinivasan received the B.E. degree in Electronics and Communication Engineering from the National Institute of Technology and Science, University of Madras, Chennai (Madras), India, in 2002. He received the M.S. degree in Electrical and Computer engineering from the Georgia Institute of Technology, Atlanta, GA, in 2004 and is currently pursuing his Ph.D. degree in Electrical and Computer Engineering at the Georgia Institute of Technology, Atlanta, GA. His research interests include low cost testing approaches for analog/RF and mixed-signal circuits, and improving performance of low cost testers for enabling high quality tests.Abhijit Chatterjee received the Bachelor of Technology degree in electrical engineering from the Indian Institute of Technology, Kanpur, India, in 1981, the M.S. degree in electrical engineering and computer science from University of Illinois at Chicago in 1983 and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1990. Until December 1992, he was a Research Staff Member at the General Electric Research and Development Center in Schenectady, NY. His work has been cited by the Wall Street Journal and presented on a Japanese network TV program called High Tech Shower International. He is a collaborating partner in NASAs New Millennium Project. Dr. Abhijit Chatterjee is also the author of one U.S. patent and has over one hundred publications in referenced journals and conferences.     

ITP: an image transport protocol for the Internet

Images account for a significant and growing fraction of Web downloads. The traditional approach to transporting images uses TCP, but this is overly restrictive for image data. Our analysis shows that the in-order delivery abstraction provided by a TCP-based approach prevents the receiver application from processing and rendering portions of an image when they actually arrive. Thus an image is rendered in bursts interspersed with long idle times rather than smoothly. This paper describes the design, implementation and evaluation of an image transport protocol (ITP) for image transmission over loss-prone congested or wireless networks. ITP improves user-perceived latency using application-level framing (ALF) and out-of-order application data unit (ADU) delivery, achieving significantly better interactive performance as measured by the evolution of peak signal-to-noise ratio (PSNR) with time at the receiver. ITP runs over UDP, incorporates receiver-driven selective reliability, uses a congestion manager (CM) to adapt to network congestion and is customizable for specific image formats (e.g., JPEG and JPEG2000). ITP enables a variety of new receiver post-processing algorithms such as error concealment that further improve the interactivity and responsiveness of reconstructed images. Performance experiments across a variety of loss conditions demonstrate the benefits of ITP in improving the interactivity of image downloads at the receiver     

Influence of Abrasive Properties on Residual Stresses in Lapped Ferrite and Alumina

The effect of abrasive-particle properties on surface-finishing residual stresses, surface finish, and material removal rates during the lapping of ferrite and aluminium oxide is quantified experimentally. It is shown that lapping with softer abrasives and smaller particles results in lower compressive residual stresses near the surface and improved surface finish. These results demonstrate possible methods for controlling surface finishing residual stresses in ceramics while at the same time achieving dimensional accuracy.     

FastFabric: Scaling hyperledger fabric to 20 000 transactions per second

Blockchain technologies are expected to make a significant impact on a variety of industries. However, one issue holding them back is their limited transaction throughput, especially compared to established solutions such as distributed database systems. In this paper, we rearchitect a modern permissioned blockchain system, Hyperledger Fabric, to increase transaction throughput from 3000 to 20 000 transactions per second. We focus on performance bottlenecks beyond the consensus mechanism, and we propose architectural changes that reduce computation and I/O overhead during transaction ordering and validation to greatly improve throughput. Notably, our optimizations are fully plug‐and‐play and do not require any interface changes to Hyperledger Fabric.     

Dual-mode control of tri-state boost converter for improved performance

A tri-state boost converter with an additional boost-inductor free-wheeling interval was proposed earlier to eliminate the right-half-plane (RHP) zero that occurs in the control-to-output transfer function of a classical boost converter under continuous-conduction mode of operation. A "constant-D/sub o/" control scheme, in which the "capacitor-charging" interval of the converter was kept constant, was employed. This resulted in a relatively large inductor current, especially under high line and load conditions, thereby causing high circuit losses. This paper proposes two variations of a novel dual-mode control (DMC) scheme that vary both the "boost" and the "capacitor-charging" intervals. Control analysis, design, and limitations of the proposed DMC schemes are presented. Through computer simulations and hardware experiments the performance of the tri-state boost converter with DMC schemes are compared with those of the tri-state boost converter with "constant-D/sub o/" control scheme, and the classical PI-controlled boost converter. The DMC schemes achieve a significant (about 10%) improvement in converter's efficiency for a wide load range over the "constant-D/sub o/" control scheme.     

Improved neural heuristics for multicast routing

Future networks must be adequately equipped to handle multipoint communication in a fast and economical manner. Services requiring such support include desktop video conferencing, tele-classrooms, distributed database applications, etc. In networks employing the asynchronous transfer mode (ATM) technology, routing a multicast is achieved by constructing a minimum cost tree that spans the source and all the destinations. When the network is modeled as a weighted, undirected graph, the problem is that of finding a minimal Steiner tree for the graph, given a set of destinations. The problem is known to be NP-complete. Consequently, several heuristics exist which provide approximate solutions to the Steiner problem in networks, We show how the random neural network (RNN) can be used to significantly improve the quality of the Steiner trees delivered by the best available heuristics which are the minimum spanning tree heuristic and the average distance heuristic. We provide an empirical comparison and find that the heuristics which are modified using the neural network yield significantly improved trees     

Automatic mesh generation using the symmetric axis transformationof polygonal domains

An automatic method for generating finite element meshes for multiply connected planar domains with polygonal boundaries (i.e. planar polygons with polygonal holes) is described. The symmetric axis transform is used to obtain a planar graph that partitions the given domain. This transformation may introduce edges in the graph that are too long or too short for generating good meshes. A silver processing algorithm, which transforms the graph into another graph devoid of such edges, is presented. Finally, additional modes are placed on the edges of the graph to obtain a triangulation, and this process is applied iteratively, yielding the final mesh. The method automatically increases the mesh density in regions of rapid change in shape and allows both global and local control of the mesh density. The method also admits the imposition of node compatibility constraints along domain boundaries, thus making the method suitable for meshing planar cell complexes (i.e multiple polygonal domains with shared boundaries in two-dimensional space) and for generating boundary elements for polyhedra in three-dimensional space     

BIST/Digital-Compatible Testing of RF Devices Using Distortion Model Fitting

Testing of Radio Frequency (RF) circuits for nonlinearity specifications generally requires the use of multiple test measurements thereby contributing to increased test cost. Prior RF test methods have suffered from significant test calibration effort (training for supervised learners) when using compact tests or from increased test time due to direct specification measurement. On the other hand, due to aggressive technology scaling, there are plenty of digital transistors available that can be used to simplify testing of Analog/Mixed-Signal (AMS) and RF devices. In this paper, an RF test methodology is developed that: (a) allows RF devices to be tested for several distortion specifications using distortion model fitting algorithms in test time comparable to what can be achieved using supervised learning techniques while retaining the accuracy of direct specification measurement, (b) allows multiple RF specifications to be determined concurrently from a single data acquisition and (c) allows digital-compatible testing/BIST to be performed using digital testers or on-chip built in self-test (BIST) circuitry. With regard to (a), a key benefit is that no training of supervised learning algorithm is necessary. The proposed method based on distortion model fitting is shown to give excellent results across common RF performance metrics while providing ~10× improvements in test time compared to previous methods.     

Interfacial layer quality effects on low-frequency noise (1/f) in p-MOSFETs with advanced gate stacks

The effects of interfacial layer quality on the low-frequency noise behavior of p-channel MOSFETs with high-κ gate dielectric and metal gate are investigated. Devices with chemically grown SiO₂ interfacial layers (0.8 nm) are compared with N₂O (0.8 nm) interfacial oxides. A 0.4 nm SiO₂ interfacial layer device is used for comparison purposes. A cross-over kind of behavior has been observed in N₂O devices, which occur at lower gate voltages (1.2–1.3 V) when normalized spectral densities and input referred noise are investigated. This behavior is found to be closely related to the observed transconductance variation in these devices. The dominant mechanism of 1/f noise is found to be Hooge’s mobility fluctuations. Hooge’s parameter, as a figure of merit, shows an increase for 0.4 nm devices when compared to 0.8 nm devices, while 0.8 nm N₂O devices confirm their cross-over nature.