Traffic differentiation support in vehicular delay-tolerant networks

Vehicular Delay-Tolerant Networking (VDTN) is a Delay-Tolerant Network (DTN) based architecture concept for transit networks, where vehicles movement and their bundle relaying service is opportunistically exploited to enable non-real time applications, under environments prone to connectivity disruptions, network partitions and potentially long delays. In VDTNs, network resources may be limited, for instance due to physical constraints of the network nodes. In order to be able to prioritize applications traffic according to its requirements in such constrained scenarios, traffic differentiation mechanisms must be introduced at the VDTN architecture. This work considers a priority classes of service (CoS) model and investigates how different buffer management strategies can be combined with drop and scheduling policies, to provide strict priority based services, or to provide custom allocation of network resources. The efficiency and tradeoffs of these proposals is evaluated through extensive simulation.     

Genetic-based random key generator (GRKG): a new method for generating more-random keys for one-time pad cryptosystem

In this paper, a new algorithm for generating more-randomized keys for symmetrical cipher one-time pad (OTP) according to the linear congruential (LCG) method based on the idea of genetic algorithm is proposed. The method, genetic-based random key generator, is proposed for generating keys for the OTP method with a high degree of key randomness; this adds more strength to the OTP method against breaking this cryptosystem. This algorithm is composed of two parts. Initially, the first population is being generated by LCG method, and then, genetic operators for generating the next populations are being used. Generating random keys with the presented method requires seven-parameter key that increases the security of communication between the transceivers.     

Simulation of UV photoreactor for water disinfection in Eulerian framework

A novel computational fluid dynamic (CFD) modeling procedure was developed in order to simulate ultraviolet (UV) photoreactors in the Eulerian framework. In this procedure, the governing equations of radiation distribution, mass conservation, momentum conservation, and species mass conservation are solved together in order to determine the radiant energy field, velocity field, and the concentration profile of microorganisms at steady state conditions. The general method presented can be employed to derive the volumetric inactivation rate and the theoretical efficiency of a UV photoreactor. The integrated CFD model of UV photoreactor performance was successfully evaluated with experimental biodosimetry results. The verified procedure can be applied to the simulation and design optimization of UV photoreactors with different geometries and operating conditions.     

Sarcoidosis manifesting as uveitis and menometrorrhagia

PURPOSE: To report a rare systemic manifestation of sarcoidosis identified in a 47-year-old white woman while she was undergoing evaluation for bilateral recurrent uveitis. METHODS: The patient underwent clinical and laboratory evaluation for bilateral recurrent uveitis including serologic and radiologic testing, a gallium scan, and an endometrial biopsy. RESULTS: Although the serologic tests and chest x-ray were normal, the gallium scan was consistent with sarcoidosis, and the endometrial biopsy provided a tissue diagnosis. CONCLUSION: Sarcoidosis involving the female reproductive tract is rare. A thorough review of systems is crucial in the evaluation of any patient with recurrent uveitis.     

A semi-theoretical and experimental approach for the determination of the stress intensity factors

The stress intensity factors for plexiglass plates containing edge cracks and subjected to either pure bending or tension are determined herein. The method of investigation was based on a semi-theoretical and experimental approach, where the stress intensity factors are expressed in terms of the measured diameter of the caustic, the crack length, and the width of the specimen. First, two basic crack arrangements (single and double edge cracks) were studied and then the method was utilized for the investigation of more complicated crack arrangements which are difficult or maybe impossible to be investigated otherwise. In particular, the stress intensity factor for plates having a sharp V-notch of various angles θ, and semi-infinite plates containing equal parallel edge cracks subjected to pure bending and tension respectively, were investigated in order to verify the validity of this method.     

Theoretical Study of RF Breakdown in GaN Wurtzite and Zincblende Phase MESFETs

In this paper, we present a comparison of the RF breakdown behaviors of representative wurtzite and zincblende phase GaN MESFET structures based on a theoretical analysis. The calculations are made using a full band ensemble, Monte Carlo simulation that includes a numerical formulation of the impact ionization transition rate. Calculations of the RF breakdown voltages are presented for submicron MESFET devices made from either wurtzite or zincblende phase GaN. The devices are otherwise identical. It is found that the RF-breakdown voltage of the devices increases with increasing frequency of the applied large signal RF excitation.     

A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices

This paper extends the timing test model in [5] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures' impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, Parallel/Serial RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a test escape of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter. Baosheng Wang received his B.S. degree from Beijing University of Aeronautics and Astronautics (BUAA), Beijing, P.R. China, in 1997 and M.S. degree from Precision Instrument & Mechanical Engineering from the Tsinghua University, Beijing, P. R. China in 2000. In 2005, he received his Ph.D. degree in Electrical Engineering from the University of British Columbia (UBC), Vancouver, BC, Canada. During his Master study, he was doing MEMS, Micro Sensors and Digital Signal processing. From 2000 to 2001, he worked in Beijing Gaohong Telecommunications Company as a hardware engineer in ATM technology. Currently, he is a Design-for-Test (DFT) engineer at ATI Technologies Inc., Markham, Ontario, Canada. He publishes widely at international conferences and journals. His primary research interests are time-driven or timing-oriented testing methodologies for System on-a-Chip (SoC). These fields include test time reduction for SRAMs, accelerated reliability test for non-volatile memories, yield analysis for SoC timing tests, SoC path delay timing characterization and embedded timing measurements. Andy Kuo is currently a Ph.D student of System on a Chip (SoC) Research Lab at the Department of Electrical and Computer Engineering, University of British Columbia. He received his M.A.Sc. and B.A.Sc in electrical and computer engineering from University of British Columbia and University of Toronto in 2004 and 2002 respectively. His research interests include high-speed signal integrity issues, jitter measurement, serial communications. Touraj Farahmand received the B.Sc. degree in Electrical Engineering from Esfahan University of Technology, Esfahan, Iran in 1989 and the M.Sc. in Control Engineering from Sharif university of Technology, Tehran, Iran in 1992. After graduation, he joined the Electrical and Computer Research center of Esfahan University of Technology where he was involved in the DSP algorithm development and design and implementation of the control and automation systems. Since October 2001, he has been working in the area of high-speed signal timing measurement at SoC (System-on-a-Chip) lab of UBC (University of British Columbia) as a research engineer. His research interests are signal processing, jitter measurement, serial communication and control. André Ivanov is Professor in the Department of Electrical and Computer Engineering, at the University of British Columbia. Prior to joining UBC in 1989, he received his B.Eng. (Hon.), M. Eng., and Ph.D. degrees in Electrical Engineering from McGill University. In 1995–96, he spent a sabbatical leave at PMC-Sierra, Vancouver, BC. He has held invited Professor positions at the University of Montpellier II, the University of Bordeaux I, and Edith Cowan University, in Perth, Australia. His primary research interests lie in the area of integrated circuit testing, design for testability and built-in self-test, for digital, analog and mixed-signal circuits, and systems on a chip (SoCs). He has published widely in these areas and holds several patents in IC design and test. Besides testing, Ivanov has interests in the design and design methodologies of large and complex integrated circuits and SoCs. Dr. Ivanov has served and continues to serve on numerous national and international steering, program, and/or organization committees in various capacities. Recently, he was the Program Chair of the 2002 VLSI Test Symposium (VTS'02) and the General Chair for VTS'03 and VTS'04. In 2001, Ivanov co-founded Vector 12, a semiconductor IP company. He has published over 100 papers in conference and journals and holds 4 US patents. Ivanov serves on the Editorial Board of the IEEE Design and Test Magazine, and Kluwer's Journal of Electronic Testing: Theory and Applications. Ivanov is currently the Chair of the IEEE Computer Society's Test Technology Technical Council (TTTC). He is a Golden Core Member of the IEEE Computer Society, a Senior Member of the IEEE, a Fellow of the British Columbia Advanced Systems Institute and a Professional Engineer of British Columbia. Yong Cho received the B.S. degree from Kyung Pook National Unviersity, Korea, in 1981 and the M.S. degree from in electrical and computer engineering from the University of South Carolina, Columbia, S.C., in 1988 and the Ph.D. degree in electrical engineering and applied physics from Case Western Reserve University, Cleveland, OH, in 1992. He is currently a Professor with the Department of Electronics Engineering, Konkuk University, Seoul, Korea. His recent research interests include SoC Design and Verification, H/W and S/W co-design, and embedded programming on SoC. Sassan Tabatabaei received his PHD in Electrical Engineering from the University of British Columbia, Vancouver, Canada in 2000. Since then, he has held several senior technical positions at Vector12 Corp, Guide Technology, and Virage Logic. His professional and research interests include mixed-signal design and test, and signal integrity and jitter test methodologies for high-speed circuits and multi-Gbps serial interfaces. He has published several papers and holds a US patent in the area of timing and jitter measurement. Currently, he holds the position of the director for embedded test at Virage Logic Corporation.     

A two dimensional investigation on plates with oblique equal and unequal parallel edge cracks subjected to tension

This paper reports on an attempt to investigate the stress intensity factors of equal and unequal oblique parallel edge cracks subjected to tension. The effects of the variation of the length of the cracks, angle of inclination, and crack spacings on the stress intensity factors (opening and sliding modes) were studied. Experimental observations show that, for crack spacings equal or larger than the length of the equal oblique parallel edge cracks, the size of the caustics for the cracks in the loaded specimen approach that of a single oblique edge crack with the same angle of inclination.In the case of unequal oblique parallel edge cracks, a crack closure phenomenon and its occurrance with respect to the length of the cracks and crack spacings were investigated. It was observed that the transverse diameter of the caustic for the shorter cracks became small and negligible when the position of the shorter cracks with respect to the longer cracks became smaller than half of the crack spacings.

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Résumé Le mémoire est relatif à une tentative d'étude des facteurs d'intensité de contrainte relatifs à des fissures de bord parallèles et obliques de longuers égales et inégales soumises à tension. On étudie les effets de la variation de longueurs des fissures, de l'angle de leur inclinaison, et de la distance entre les fissures sur les facteurs d'intensité de contrainte dans les modes d'ouverture et de glissement. Les observations expérimentales montrent que lorsque les fissures sont espacées d'une grandeur égale ou supérieure à la longueur des fissures de bord obliques parallèles et égales, la dimension des caustiques relatives aux fissures dans une éprouvette sous charge est proche de celle relative à une fissure de bord simple oblique possédant le même angle d'inclinaison.Dans le cas de fissures de bords parallèles obliques inégales, un phénomène de fermeture de fissure a été étudié, ainsi que son apparition en fonction de la longueur des fissures et de l'espacement entre celles-ci. Il a été observé que le diamètre transversal de la caustique relative aux fissures plus courtes devient faible et négligeable lorsque la position des fissures courtes par rapport aux fissures les plus longues devient plus petite que la moitié de l'espacement entre les fissures.