Integrating IPsec within OpenFlow Architecture for Secure Group Communication

Network securityprotocolssuch as IPsechave been used for many years to ensure robust end-to-end communication and are impor-tant in the context of SDN.Despite the widespread installation of IPsec to date,per-packet protection offered by the protocol isnot very compatible with OpenFlow and flow-like behavior.OpenFlow architecture cannot aggregate IPsec-ESP flows in transportmode or tunnel mode because layer-3 information is encrypted and therefore unreadable.In this paper,we propose using the Secu-rity Parameter Index(SPI)of IPsec within the OpenFlow architecture to identify and direct IPsec flows.Thisenables IPsec to con-form to the packet-based behavior of OpenFlow architecture.In addition,by distinguishing between IPsec flows,the architectureis particularly suited to secure group communication.     

Effect of Channel Estimation Error on Time Reversal UWB Communication System

In this paper, effects of channel estimation error on time reversal (TR) UWB systems are investigated. In time reversal, a signal is prefiltered by using a time reversed complex conjugate of the channel impulse response as a transmitter prefilter. To investigate the effect of channel estimation error, an error function is added to TR-UWB prefilter. Analytical and simulation results show that channel estimation error degrade the performance. The signal-to-interference plus noise ratio decreases with increasing error variance. It is shown that the channel performance is degraded about 0.5 dB in CM1 and 1.3 dB in CM4 channel.     

Cramer–Rao bound and minimum variance unbiased estimator for joint sampling clock offset and channel taps in MC‐CDMA systems

Exact closed‐form expressions of the Cramer–Rao bound (CRB) for joint sampling clock offset and channel taps are obtained in multi‐carrier code division multiple access systems. CRB is undoubtedly the most well known variance's bound to determine. It provides a benchmark against which we can compare the performance of any unbiased estimator. Furthermore, minimum variance unbiased (MVU) estimator for these parameters is proposed. Moreover, maximum likelihood (ML) and least‐squares estimators for joint sampling clock offset and channel taps are presented. Best linear unbiased estimator is also introduced just for channel taps. The performances of the estimators are compared through simulation results with the proposed CRB. Our results show the better performances of MVU and ML estimators with more computational complexity compared with the others. Copyright © 2008 John Wiley & Sons, Ltd.     

Blind separation of image sources via adaptive dictionary learning

Sparsity has been shown to be very useful in source separation of multichannel observations. However, in most cases, the sources of interest are not sparse in their current domain and one needs to sparsify them using a known transform or dictionary. If such a priori about the underlying sparse domain of the sources is not available, then the current algorithms will fail to successfully recover the sources. In this paper, we address this problem and attempt to give a solution via fusing the dictionary learning into the source separation. We first define a cost function based on this idea and propose an extension of the denoising method in the work of Elad and Aharon to minimize it. Due to impracticality of such direct extension, we then propose a feasible approach. In the proposed hierarchical method, a local dictionary is adaptively learned for each source along with separation. This process improves the quality of source separation even in noisy situations. In another part of this paper, we explore the possibility of adding global priors to the proposed method. The results of our experiments are promising and confirm the strength of the proposed approach.     

SpecSyn: an environment supporting the specify-explore-refineparadigm for hardware/software system design

System-level design issues are gaining increasing attention, as behavioral synthesis tools and methodologies mature. We present the SpecSyn system-level design environment, which supports the new specify-explore-refine (SER) design paradigm. This three-step approach to design includes precise specification of system functionality, rapid exploration of numerous system-level design options, and refinement of the specification into one reflecting the chosen option. A system-level design option consists of an allocation of system components, such as standard and custom processors, memories, and buses, and a partitioning of functionality among those components. After refinement, the functionality assigned to each component can then he synthesized to hardware or compiled to software. We describe the issues and approaches for each part of the SpecSyn environment. The new paradigm and environment are expected to lead to a more than ten times reduction in design time, and our experiments support this expectation     

Near Optimum Random Routing of Uniformly Load Balanced Nodes in Wireless Sensor Networks Using Connectivity Matrix

Wireless Personal Communications - Wireless sensor networks (WSNs) are ad hoc networks usually made up of miniaturized autonomous units called sensor nodes that communicate in between by radio...     

Mlcrolasers based on silica microspheres

Light can be confined efficiently in the high-Q, small-volume whispering-gallery-modes observed in silica microspheres. By coupling these microspheres to eroded optical fibers and fiber tips, direct mapping of the whispering-gallery modes has been achieved and the mode numbers have been assessed. The properties of these modes have allowed us to obtain laser action with very low thresholds in Nd-doped silica microspheres. Further projects in the field of non-linear optics and cavity quantum electrodynamics are described.     

Extending the Kernighan/Lin Heuristic for Hardware and Software Functional Partitioning

The Kernighan/Lin graph partitioning heuristic, also known as min-cut or group migration, has been extended over several decades very successfully for circuit partitioning. Those extensions customized the heuristic and its associated data structure to rapidly compute the minimum-cut metric central to circuit partitioning; as such, those extensions are not directly applicable to other problems. In this paper, we extend the heuristic for functional partitioning, which in turn can solve the much investigated codesign problem of partitioning a system's coarse-grained functions among hardware and software components. The key extension customizes the heuristic and data structure to rapidly compute execution-time and communication metrics, crucial to hardware and software partitioning, and leads to near-linear time-complexity and excellent resulting quality. Another extension uses a new criteria for terminating the heuristic, eliminating time-consuming and unnecessary fine-tuning of a partition. Our experiments demonstrate extremely fast execution times (just a few seconds) with results matched only by the slower simulated annealing heuristic, meaning that the extended Kernighan/Lin heuristic will likely prove hard to beat for hardware and software functional partitioning.     

A novel low-power full-adder cell for low voltage

This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the time-consuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-μm CMOS process technology. The adder cell is compared with seven widely used adders based on power consumption, speed, power-delay product (PDP) and area efficiency. Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has more than 11% in power savings over a conventional 28-transistor CMOS adder. In addition, it consumes 30% less power than transmission function adder (TFA) and is 1.11 times faster.