A radix-8 wafer scale FFT processor

Wafer Scale Integration promises radical improvements in the performance of digital signal processing systems. This paper describes the design of a radix-8 systolic (pipeline) fast Fourier transform processor for implementation with wafer scale integration. By the use of the radix-8 FFT butterfly wafer that is currently under development, continuous data rates of 160 MSPS are anticipated for FFTs of up to 4096 points with 16-bit fixed point data.     

Miniaturized Microstrip Patch Antenna Array for ISM Band Using Complementary Split Ring Resonator

Wireless Personal Communications - These days patch antenna arrays are widely used in various communication systems. In this research design of miniaturized microstrip patch antenna array is...     

MiniPCI、PCMCIA模块打头阵：WiMAX推进商品化速度

在硝烟弥漫的宽带战场,强大的网络接入能力、低成本、高收益等优点无疑是竞争力所在.WiMAX可作为无线DSL或无线Cable技术来弥补有线技术的不足,同时也被部分业界人士视作新一移动基础设施或第四代无线移动应用的互补技术.目前OEM、ODM相关发展厂商正通过采用具弹性系统架构的ASIC以降低成本,加速WiMAX技术推向市场的时间.     

Silicon Nitride Derived from an Organometallic Polymeric Precursor: Preparation and Characterization

Partially crystalline Si₃N₄, with nanosized crystals and a specific surface area greater than 200 m²/g, is obtained by pyrolysis of a commercially available vinylic polysilane in a stream of anhydrous NH₃ to 1000°C. This polymer does not contain N initially. Crystallization to high-purity α-Si₃N₄ proceeds with additional heating above 1400°C under N₂. The changes in crystallinity, powder morphology, infrared spectra, and elemental compositions, for samples annealed from 1000° to 1600°C under N₂, are consistent with an amorphous-to-crystalline transformation. Although macroscopic consolidation and local densification occur at 1400°C, volatilization and accompanying weight loss limit bulk densification. The effect of temperature on specific surface area is examined and related to the sintering process. These results are applicable to pyrolysis, decomposition, and crystallization studies of ceramics synthesized by polymeric precursor routes.     

High Performance Process Variations Aware Technique for Sub-threshold 8T-SRAM Cell

The demand of low power high density integrated circuits is increasing in modern battery operated portable systems. Sub-threshold region of MOS transistors is the most desirable region for energy efficient circuit design. The operating ultra-low power supply voltage is the key design constraint with accurate output performance in sub-threshold region. Degrading of the performance metrics in Static random access memory (SRAM) cell with process variation effects are of major concern in sub-threshold region. In this paper, a bootstrapped driver circuit and a bootstrapped driver dynamic body biasing technique is proposed to assist write operation which improves the write-ability of sub-threshold 8T-SRAM cell under process variations. The bootstrapped driver circuit minimizes the write delay of SRAM cell. The bootstrapped driver dynamic body bias increases the output voltage levels by boosting factor therefore increasing in switching threshold voltage of MOS devices during hold and read operation of SRAM latch. The increment in threshold voltage improves the static noise margin and minimizing the process variation effects. Monte-Carlo simulation results with 3 \(\sigma \) Gaussian distributions show the improvements in write delay by 11.25 %, read SNM by 12.20 % and write SNM by 12.57 % in 8T-SRAM cell under process variations at 32 nm bulk CMOS process technology node.     

Weight loss in frankfurters during thermal processing

A simplified two-term model was developed to predict the weight loss of frankfurters during thermal processing at various process conditions and with various product compositions. The model was validated with the experimental data. The moisture loss rate was found to be proportional to product temperature and inversely proportional to the fat-protein ratio of the product.     

Digital signal propagation delay in a nano-circuit containing reactive and resistive elements

The transient switching delay in a micro/nano-scale circuit containing resistive and reactive elements are sternly affected by the surge in the resistance arising from sub-linear current-voltage (I-V) characteristics limited by the velocity and current saturation. The saturation arises due to the realignment of randomly oriented velocity vectors to the unidirectional streamlined ones in a high electric field when voltage applied across a resistor exceeds its decreasing critical value with reduced channel length. The frequency response f = 1/2πτ_t is affected by a transit time delay τ_t is lower than that predicted from the application of Ohm’s law. The resistance surge dramatically boosts the RC time constant and switching delay and attenuates the L/R time constant and switching delay.     

The Asymmetric Golden Code for Fast Decoding on Time-Varying Channels

The golden code is a full-rate full-diversity space–time code for the two-input two-output channel with good performance but high decoding complexity. The overlaid Alamouti codes were recently proposed as an alternative; in exchange for a slight performance penalty, they have lower decoding complexity on quasistatic channels with QAM alphabets. However, the complexity advantage of the overlaid codes vanishes for time-varying channels. This paper proposes the asymmetric golden code, a novel full-rate and full-diversity space–time code for the two-input two-output channel that offers reduced-complexity decoding on both quasistatic and time-varying channels.     

The design and evaluation of an end-to-end handoff management protocol

We introduce an efficient protocol for end-to-end handoff management in heterogeneous wireless IP-based networks. The protocol is based on the stream control transmission protocol (SCTP), and employs a soft-handoff mechanism that uses end-to-end semantics for signaling handoffs and for transmitting control messages. The design goal of this protocol is twofold—first, to reduce the home registration delay, and, second, to eliminate the tunnelling cost which exists in current proposals, such as Mobile IP and its derivatives. Furthermore, we propose successive enhancements to the initial mobility management framework for achieving better scalability. We present strong analytical and simulation-based results that show performance improvements over existing approaches. Antonios Argyriou is a Ph.D. candidate in the school of electrical and computer engineering, Georgia Institute of Technology. He received his M.S. degree from the Georgia Institute of Technology in 2003, and the diploma from Democritus University of Thrace in 2001, both in electrical and computer engineering. His research interests spawn in all aspects of computer networking while specific interests include wireless networks and multimedia communications. He is a student member of IEEE and ACM. Vijay Madisetti is a professor of electrical and computer engineering at the Georgia Institute of Technology. He splits his time among teaching, research and entrepreneurship. His interests are design, prototyping, and packaging of electronic systems, virtual prototyping, embedded software systems, and computer networks. He obtained his Ph.D. in electrical engineering and computer science from the University of California at Berkeley. He is a member of the IEEE and the Computer Society.