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21.
The reuse of scientific knowledge obtained from one investigation in another investigation is basic to the advance of science. Scientific investigations should therefore be recorded in ways that promote the reuse of the knowledge they generate. The use of logical formalisms to describe scientific knowledge has potential advantages in facilitating such reuse. Here, we propose a formal framework for using logical formalisms to promote reuse. We demonstrate the utility of this framework by using it in a worked example from biology: demonstrating cycles of investigation formalization [F] and reuse [R] to generate new knowledge. We first used logic to formally describe a Robot scientist investigation into yeast (Saccharomyces cerevisiae) functional genomics [f1]. With Robot scientists, unlike human scientists, the production of comprehensive metadata about their investigations is a natural by-product of the way they work. We then demonstrated how this formalism enabled the reuse of the research in investigating yeast phenotypes [r1 = R(f1)]. This investigation found that the removal of non-essential enzymes generally resulted in enhanced growth. The phenotype investigation was then formally described using the same logical formalism as the functional genomics investigation [f2 = F(r1)]. We then demonstrated how this formalism enabled the reuse of the phenotype investigation to investigate yeast systems-biology modelling [r2 = R(f2)]. This investigation found that yeast flux-balance analysis models fail to predict the observed changes in growth. Finally, the systems biology investigation was formalized for reuse in future investigations [f3 = F(r2)]. These cycles of reuse are a model for the general reuse of scientific knowledge.  相似文献   
22.
介绍了有限元软件在大功率LED封装热分析中的应用,对一种多层陶瓷金属(MLCMP)封装结构的LED进行了热模拟分析,比较了不同热沉材料的散热性能,模拟了输入功率以及强制空气冷却条件对芯片温度的影响.结果表明当达到热稳态平衡时,芯片上的温度最高,透镜顶部表面的温度最低,当输入功率达到3 W时,芯片温度超过了150℃,强制空冷能显著改善器件的散热性能.  相似文献   
23.
A 0.9-1.6-V, 1-MHz, 8-b microcontroller based on the 68HC08 architecture is presented. In addition to standard digital microcontroller functions, the chip features RAM, ROM, phase-locked loop (PLL) clock synthesis, and liquid crystal displays (LCD) drive capabilities operating from the voltage supply range of a single AA or AAA battery. The design used a library of CMOS microcontroller building blocks, converted into a low-voltage technology using unilateral transistors. The design approach was to optimize the conversion strategy for each functional block and to provide new designs when the conversion was insufficient. The chip exceeded specifications with blocks showing full functionality down to 0.7 V  相似文献   
24.
In his remarks on the comments by Yokoyama (see ibid., vol.43, no.5, p.541-42, 1995) and the reply by King and Sandler (see ibid., vol.43, no.5, p.542-44, 1995) regarding our paper (see ibid., vol.42, no.3, p.382-9, 1994) J. R. Wait (see ibid., vol.44, no.2, p.271-72, 1996) makes a number of statements that require correction. These are considered in turn, but since they all center about the definition of the Sommerfeld numerical distance, this is introduced first. In a paper by Norton (1937), which is later quoted and applied by Wait, a formula is given for the generalized numerical distance for the height z and radial distance ρ due to a vertical dipole at the height d in the air (region 2, real wave number kz) over a conducting or dielectric region 1 (complex wave number k1). It is important to emphasize that the purpose of this response is not to belittle the important pioneer work of Norton, Wait, and others. Interest a half century ago was in communication over the surface of the Earth and sea with (z+d)2≪ρ2. In this range, their formulas are accurate. However, recent progress which eliminates the restriction (z+d)2≪ρ2 or k2ρ≫1 should not be ignored by blindly using restricted formulas where they do not apply  相似文献   
25.
26.
A new NAND-type nonvolatile memory with a field-enhancing tip structure embedded in low-temperature polycrystalline silicon (LTPS) panel was demonstrated on a glass substrate for the first time. A thin-film transistor (TFT) metal-oxide-nitride-oxide-silicon (MONOS) device based on sequential lateral solidification crystallization with a fully depleted poly-Si channel, an oxide-nitride-oxide stack gate dielectric, and a metal gate is integrated into a NAND array. A NAND test array based on p-channel LTPS TFTs exhibits good cycling endurance and data retention properties and negligible program and read disturbance. These results strongly support the claim that this TFT-MONOS device is a promising candidate for use in embedded nonvolatile memory for system-on-panel and 3-D IC applications  相似文献   
27.
Studies of parental mediation of children's television viewing have included samples of mostly middle- and upper-class Caucasian parents. These studies have only begun to examine mediation in the context of parent-child relationships. This study of 306 low-income, predominately African American mothers assesses macro- and microlevel influences on viewing mediation using Bronfenbrenner's ecological theory of child development. It was hypothesized that factors outside the home (e.g., work hours) influence parents' involvement with children, which, in turn, was predicted to influence viewing mediation. Results supported this model for coviewing and instructive mediation, but not for viewing restrictions.  相似文献   
28.
Clad-pumped Yb,Er codoped fiber lasers   总被引:7,自引:0,他引:7  
Double-clad and Yb,Er codoped fiber lasers emitting at eye-safe wavelengths (>1.5 μm) have been investigated by varying the codopant concentrations, core modifiers, fiber length, and the spectrum of the diode pump. With a proper composition, the laser output contains only one lasing wavelength, at 1.6 μm. Highest slope efficiency greater than 60% for this three-level system, emitting only at 1.6 μm, has been obtained by using a 20-m-long, double-clad and codoped fiber with the core and clad diameters of 6.3 and 300 μm, respectively. By tradeoff of slope efficiency fur higher output power, a 30-m-long fiber is considered to be the best choice  相似文献   
29.
Sub-50 nm P-channel FinFET   总被引:6,自引:0,他引:6  
High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an Idsat of 820 μA/μm at Vds=Vgs=1.2 V and T ox=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm  相似文献   
30.
The effects of Saponin alone and in combination with antimony and glue on zinc deposition current efficiency and polarization and on the morphology and orientation of 6h and 24h zinc deposits electrowon at 500 A m–2 and 38°C from Kidd Creek zinc electrolyte were determined. Saponin, at concentrations to 100mgl–1, was weakly polarizing, changed the preferred deposit orientation from basal to intermediate and decreased the current efficiency. At optimum glue + antimony levels, Saponin concentrations 5mgl–1 resulted in an increase in zinc deposition current efficiency and consistently gave either a <114><112><103><102><101> or a <101><112> preferred deposit orientation depending on the antimony + glue combination used. Tests run for 24h for selected combinations of Saponin, antimony and glue confirmed the results obtained for the 6h studies.  相似文献   
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