A New Secure Authenticated Group Key Transfer Protocol

Group key transfer protocols depend on a mutually trusted key generation center (KGC) to generate group keys and transport group keys to all group members secretly. Generally, KGC encrypts group keys under another secret key shared with each user during registration. In this paper, we propose a novel secure authenticated group key transfer protocol using a linear secret sharing scheme (LSSS) and ElGamal cryptosystem, where KGC broadcasts group key information to all group members. The confidentiality of this transformation is guaranteed by this LSSS and ElGamal cryptosystem. We also provide authentication for transporting this group key. Goals and security threats of our protocol are analyzed in detail.     

CMOS dual-band variable-gain amplifier for 3G-WCDMA and WLAN dual-mode RF receivers

A dual-band variable-gain amplifier (DBVGA) is presented for integrated 2.2 GHz 3G-WCDMA and 5.2 GHz WLAN transceivers. DBVGA employs a DC-and-RF current steering technique for gain control, which can minimise variations of the noise, 1 dB gain compression point, and input/output impedance when the gain is tuned. The appropriate frequency operation band of DBVGA is jointly controlled by the switched-resonator load and the input stage gate bias, resulting in high cross-band isolation and out-of-band interference rejection. All circuits except the input stages are reused for both bands to have high component reuse. A fully-integrated 0.18 mum CMOS DBVGA has been implemented to verify the proposed design     

ZnO TFT Devices Built on Glass Substrates

ZnO thin-film transistors (TFTs) were built on glass substrates. The device with a top gate configuration operates in the depletion mode. The ZnO channel was grown by metalorganic chemical vapor deposition (MOCVD) on glass at low temperature. SiO₂ was used as the gate dielectric. The TFT has an on/off ratio of ∼4.0 × 10⁴ and a channel field-effect mobility of ∼4.0 cm²/V s. The average transmittance of the ZnO film in the visible wavelength is ∼80%. To compare the characteristics of the TFTs prepared by using a poly-ZnO and epitaxial-ZnO channel, an epi-ZnO TFT with the same configuration and dimensions was made on an r-Al₂O₃ substrate. The epi-ZnO TFT shows higher field-effect mobility of ∼35 cm²/V s and on/off ratio of ∼10⁸.     

The Economical PAPR Minization Scheme for Combinative Coding Technique Applied OFDM Communication System

In this paper, we propose a new combinative scheme to combine with parity check and block coding methods for the reduction of the peak to average power ratio (PAPR) of orthogonal frequency division multiplexing (OFDM) system. In the proposed schemes, the simulation results shown that Peak-to-Average Power Ratio (PAPR) can be reduced by 3.502 dB. The results of this mapped can be shown that PAPR is reduced. The principle of the scheme is illustrated with the specific example of an eight-carriers signal and its computer simulation results. All simulation results have compare with ideal channel case and AWGN case separately; both of cases are shown the PAPR reduced indeed. Do Horng Guo received his B.S. Degree in Electronic Engineering from National Taiwan Marine Science University, Keelung, Taiwan, in 1983, and M.S. Degree in Computer Communication from Northrop University, Los Angeles, USA, in 1986. He is enrolled in Ph.D program in Graduate Institute of Communication Engineering of Tatung University from 2001. His current interest includes wireless communication system and digital signal processing. Chau-Yun Hsu received his B.S. degree M.S. and Ph.D in Electrical Engineering from Tatung Institute of Technology, Taipei, Taiwan, in 1981, 1983 and 1988, respectively. He was the lecturer in Department of Electrical Engineering of Tatung University from 1983 to 1985. From 1988 to 1997, he served as the Associate professor of Tatung University. Since 1998, he has been the Chair Professor of Graduate Institute of Communication Engineering of Tatung University. Now he is also the chair of department of Electrical Engineering of Tatung University. His current interest includes Wireless Channel Model and Estimation, Machine Learning, Digital Signal Processing and Image Processing.     

Defect Engineering in Ambipolar Layered Materials for Mode-Regulable Nociceptor

Defect engineering represents a significant approach for atomically thick 2D semiconductor material development to explore the unique material properties and functions. Doping-induced conversion of conductive polarity is particularly beneficial for optimizing the integration of layered electronics. Here, controllable doping behavior in palladium diselenide (PdSe₂) transistor is demonstrated by manipulating its adatom-vacancy groups. The underlying mechanisms, which originate from reversible adsorption/desorption of oxygen clusters near selenide vacancy defects, are investigated systematically via their dynamic charge transfer characteristics and scanning tunneling microscope analysis. The modulated doping effect allows the PdSe₂ transistor to emulate the essential characteristics of photo nociceptor on a device level, including firing signal threshold and sensitization. Interestingly, electrostatic gating, acting as a neuromodulator, can regulate the adaptive modes in nociceptor to improve its adaptability and perceptibility to handle different danger levels. An integrated artificial nociceptor array is also designed to execute unique image processing functions, which suggests a new perspective for extension of the promise of defect engineered 2D electronics in simplified sensory systems toward use in advanced humanoid robots and artificial visual sensors.     

Analysis and design of coplanar waveguide-fed slot antenna array

A method for analyzing and designing the slot antenna array excited by a coplanar waveguide (CPW) is presented. The slots are etched on the conducting plane of the CPW and placed in the direction perpendicular to the transmission line. Moment-method analysis and matrix-pencil approach are adopted to calculate the scattering parameters and hence the self-admittance of each slot. The mutual admittances between the slots are calculated from the formulas derived for the complementary strip dipoles based on the reciprocity theorem and via Booker's relation. Then the transmission line theory is used to calculate the input impedance of the array, and an iterative process is employed to obtain a matched design for a desired slot-voltage distribution. A four-element slot array is fabricated and measured using this design procedure. Calculated results are in good agreement with measurements     

Blind Channel Identification for Cyclic-Prefixed MIMO-OFDM Systems with Virtual Carriers

This paper applies the repetition index scheme(RIS)to the channel identification of cyclic prefixed(CP)multiple-input multiple-output orthogonal frequency division multiplexing(MIMO-OFDM)systems with virtual carriers(VCs)in the environment of the number of receive antennas being no less than that of transmit antennas.The VCs will cause a rank deficiency problem in computing the subspace information.With the subcarrier mapping matrix,the received signal is simplified to remove the rank deficiency.We use the RIS scheme to generate many times of equivalent symbols so the channel identification can converge with few received OFDM blocks.The RIS scheme will convert the white noise into non-white noise.With the Cholesky factorization,a noise whitening technique is developed to turn the non-white noise back to white noise.We further analyze the necessary conditions of identifiability of channel estimation.Simulations are performed to show the superiority of the proposed method.     

A Signed Array Multiplier with Bypassing Logic

A low power digital signed array multiplier based on a 2-dimensional (2-D) bypassing technique is proposed in this work. When the horizontally (row) or the vertically (column) operand is zero, the corresponding bypassing cells skip redundant signal transitions to avoid unnecessary calculation to reduce power dissipation. An 8×8 signed multiplier using the 2-D bypassing technique is implemented on silicon using a standard 0.18 μm CMOS process to verify power reduction performance. The power-delay product of the proposed 8×8 signed array multiplier is measured to be 31.74 pJ at 166 MHz, which is significantly reduced in comparison with prior works.     

Electrical Percolation Behavior in Silver Nanowire–Polystyrene Composites: Simulation and Experiment

The design and preparation of isotropic silver nanowire‐polystyrene composites is described, in which the nanowires have finite L/D (< 35) and narrow L/D distribution. These model composites allow the L/D dependence of the electrical percolation threshold, ?_c, to be isolated for finite‐L/D particles. Experimental ?_c values decrease with increasing L/D, as predicted qualitatively by analytical percolation models. However, quantitative agreement between experimental data and both soft‐core and core–shell analytical models is not achieved, because both models are strictly accurate only in the infinite‐L/D limit. To address this analytical limitation, a soft‐core simulation method to calculate ?_c and network conductivity for cylinders with finite L/D are developed. Our simulated ?_c results agree strongly with our experimental data, suggesting i) that the infinite‐aspect‐ratio assumption cannot safely be made for experimental networks of particles with L/D < 35 and ii) in predicting ?_c, the soft‐core model makes a less significant assumption than the infinite‐L/D models do. The demonstrated capability of the simulations to predict ?_c in the finite‐L/D regime will allow researchers to optimize the electrical properties of polymer nanocomposites of finite‐L/D particles.