Effects of crystallographic misorientation on power loss in

The effects of the inclination angle β of the [001] axis out of the sheet plane on the thickness dependence of the power losses in     

New protection method for HVDC lines including cables

For the third project of the Hokkaido-Honshu HVDC Link in Japan, called the HVDC Link III project (rated at 250 kVDC-1200 A-300 MW), we developed an HVDC transmission line protection method based on a new working principle that allows high-speed and highly sensitive detection of faults, enhancing reliability in the supply of electric power. In general, increasing the sensitivity of relays will lead to an increased likelihood of undesired operation whereas lowering the sensitivity will impair the responsiveness of the relays. Our proposed method meets these apparently incompatible requirements very well. Basically classified as a differential scheme, the HVDC transmission line protection method compensates for a charging and discharging current that flows through the line-to-ground capacitance at times of voltage variations caused by a line fault or by the operation of DC power systems. The developed protection method is also characterized in that it uses current changes induced by voltage variations to restrain the operation of a relay. This configuration has made the proposed method far superior in responsiveness and sensitivity to the conventional protection method. A simulation using an EMTP (Electro-Magnetic Transients Program) was conducted on this method. Developed relay equipment embodying the new protection method was subjected to various verification tests, where this equipment was connected to a power system simulator, before being delivered to the HVDC Link III facility     

Expression of V642 APP mutant causes cellular apoptosis as Alzheimer trait-linked phenotype

APP is a transmembrane precursor of beta-amyloid. In dominantly inherited familial Alzheimer's disease (FAD), point mutations V6421, V642F and V642G have been discovered in APP695. Here we show that expression of these mutants (FAD-APPs) causes a clone of COS cells to undergo apoptosis associated with DNA fragmentation. Apoptosis by the three FAD-APPs was the highest among all possible V642 mutants; normal APP695 had no effect on apoptosis, suggesting that apoptosis by APP mutants in this system is phenotypically linked to the FAD trait. FAD-APP-induced apoptosis was sensitive to bcl-2 and most probably mediated by heteromeric G proteins. This study presents a model system allowing analysis of the mechanism for FAD-APP-induced cytotoxicity.     

Hot-carrier effects in scaled MOS devices

A universal guideline and state-of-the-art hot-carrier effects in scaled MOSFETs are reviewed and discussed from the viewpoints of 1) DC and AC hot-carrier effects, 2) hot-carrier detrapping phenomena, 3) mechanical stress effects on hot-carrier phenomena, and 4) hot-carrier resistant device structures.In the deep-submicron region, the hot-carrier applicable voltage is less than 3 V, so AC hot-carrier effects from the dynamic operation of actual circuits should be taken into account. Despite much experimentation and analysis, there is still no universally accepted theory that explain the AC degradation mechanism. This is because the noise caused by the wiring inductance in ULSI circuits and in measurement systems screens the intrinsic AC hot-carrier effects.Here, AC hot-carrier degradation enhanced by gate pulse-induced-noise is analyzed experimentally and theoretically. After eliminating the noise problem, it is found that AC hot-carrier degradation in LDD (Lightly doped drain) and GOLD (gate-drain overlapped device) structures can be estimated based on DC degradation in terms of the effective stress time which takes the duty ratio into account. In addition, it is found that the noise is negligible when the wiring inductance is smaller that 80 nH (250 mω), which is important for future circuit design.Furthermore, hot-carrier detrapping effects, especially in p-channel MOS devices, and hot-carrier phenomena under mechanical stress are investigated experimentally to better understand the underlying hot-carrier physics. Finally, future hot-carrier resistant device structures are discussed.     

Integrated optical devices of InGaAsP/InP heterojunction phototransistor and inner stripe light-emitting diode

New integrated optical devices combining an InGaAsP/InP HPT and an inner-stripe LED are proposed and their fabrication processes are described. The device functions of light amplification, optical bistability, and optical switching are demonstrated in the 1-μm wavelength region.     

Numerical analyses of high‐beta spherical tokamaks with varied elongation

The effect of plasma elongation on the second‐stable spherical tokamak (ST) was numerically studied using the experimentally measured pressure and current profiles of ultrahigh‐beta STs. The maximum beta of ST over 50% was obtained in the TS‐3 ST/CT experiment by applying an external toroidal field to an FRC. It was found that the marginal beta for the ballooning instability increased with the plasma elongation κ of ST. The elongated STs with κ > 2 have the magnetic shear (S)–pressure gradient (α) profiles located in the second‐stable regime for the ballooning mode and the stability margin increased with κ. The close relation between the absolute minimum‐B profile and the second stability was documented. The effect of elongation on maximum beta was observed to saturate when κ exceed 3, indicating that the optimized elongation for high‐beta STs is located around 2 < κ < 3. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 155(4): 1–6, 2006; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20132     

Metallized ultra-shallow-junction device technology for sub-0.1μm gate MOSFET's

This paper describes a new ultra-thin SOI-CMOS structure offering reduced parasitic diffusion-layer resistance. It addresses ways to deal with the ultra-shallow junctions required by sub-0.1 μm MOSFET's. Based on a CVD tungsten process we experimentally investigate the characteristics of selectively grown tungsten used in the source and drain region made in SOI layers of various thicknesses ranging from 10 to 100 nm. We also investigate certain CMOS device characteristics. The SOI-CMOS structure, with low parasitic diffusion-layer resistance and good contact characteristics for ultra-shallow junction devices exhibits superior device performance and high scalability