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31.
The magnitude of the V/sub T/ instability in conventional MOSFETs and MOS capacitors with SiO/sub 2//HfO/sub 2/ dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO/sub 2//HfO/sub 2/ interface and in the bulk of the HfO/sub 2/ layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows. 1) A defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO/sub 2//HfO/sub 2/ interface by tunneling.  相似文献   
32.
The authors have fabricated n-p-n GaAs/AlGaAs heterojunction bipolar transistors (HBTs) with base doping graded exponentially from 5×1019 cm-3 at the emitter edge to 5×1018 cm-3 at the collector edge. The built-in field due to the exponentially graded doping profile significantly reduces base transit time, despite bandgap narrowing associated with high base doping. Compared to devices with the same base thickness and uniform base doping of 1×1019 cm-3 , the cutoff frequency is increased from 22 to 31 GHz and maximum frequency of oscillation is increased from 40 to 58 GHz. Exponentially graded base doping also results ill consistently higher common-emitter current gain than uniform base doping, even though the Gummel number is twice as high and the base resistance is reduced by 40%  相似文献   
33.
The authors report the implementation of deep-submicrometer Si MOSFETs that at room temperature have a unity-current-gain cutoff frequency (fT) of 89 GHz, for a drain-to-source bias of 1.5 V, a gate-to-source bias of 1 V, a gate oxide thickness of 40 Å, and a channel length of 0.15 μm. The fabrication procedure is mostly conventional, except for the e-beam defined gates. The speed performance is achieved through an intrinsic transit time of only 1.8 ps across the active device region  相似文献   
34.
Trapping of net positive charge at low gate stress voltage, and of net negative charge at high gate stress voltage, is observed through changes in the gate-to-drain capacitance of the stressed junction. These observations can be explained in terms of electron trapping, hole trapping, and generation of acceptor-like interface states located in the upper half of the bandgap. Channel shortening is also observed and found to exhibit a logarithmic time dependence  相似文献   
35.
A series of polyurethane block copolymers based on hydroxy-terminated polydimethylsiloxane and poly(propylene glycol) soft segments of molecular weights 1818 and 2000, respectively, were synthesized. The hard segments consisted of 4,4′-diphenylnethane diisocyanate and 1,4-butanediol as the chain extender. Samples with different molar ratios were prepared. We tried to synthesize polydimethylsiloxane-based polyurethanes (PDMS-PU) containing a hard block as major fraction and a soft block as minor fraction for preparing toughened rigid systems. After a study of the pure polydimethylsiloxane-based polyurethane and poly(propylene glycol)-based polyurethane (PPG-PU), (mixed polyol)-based block copolymers and blends of PDMS-PU and PPG-PU were synthesized, and characterized by means of differential scanning calorimetry, tensile testing and scanning electron microscopy. In (mixed polyol)-based copolymers and lower hard-segment content blends, macro-phase separation occurred, but blends with higher hard-segment contents showed significant reduction in amounts of phase separation.  相似文献   
36.
The molecular mechanisms underlying the clustering and localization of K+ channels in specific microdomains on the neuronal surface are largely unknown. The Shaker subclass of voltage-gated K+ channel alpha-subunits interact through their cytoplasmic C-terminus with a family of membrane-associated putative guanylate kinases, including PSD-95 and SAP97. We show here that heterologous coexpression of either sap97 or PSD-95 with various Shaker-type subunits results in the coclustering of these proteins with the K+ channels. Mutation of the C-terminal sequence (-ETDV) of the Shaker subunit Kv1.4 abolishes its binding to, and prevents its clustering with, SAP97 and PSD-95. Whereas PSD-95 induces plaque-like clusters of K+ channels at the cell surface; however, SAP97 coexpression results in the formation of large round intracellular aggregates into which both SAP97 and the K+ channel proteins are colocalized. The efficiency of surface clustering by PSD-95 varies with different Shaker subunits: striking Kv1.4 clustering occurs in > 60% of cotransfected cells, whereas Kv1.1 and Kv1.2 form convincing clusters with PSD-95 only in approximately 10% of cells.  相似文献   
37.
38.
Translated from Khimicheskoe i Neftyanoe Mashinostroenie, No. 8, pp. 9–11, August, 1993.  相似文献   
39.
The plug loading effect occurring during the etchback of tungsten was investigated in a magnetically enhanced reactive ion etcher using SF 6/Ar mixtures. It was found that while the plug loading effect is independent of varying SF6/Ar flow rate ratio and magnetic field intensity, it is reduced under the condition of high selectivity of tungsten relative to TiN which was achieved at high chamber pressure and low RF power. It is proposed that when TiN is used as a glue layer, the W etch rate enhancement in the plug is mainly controlled by a local loading effect. Under the optimized etchback conditions the plug loss was successfully controlled without the tungsten residue left on severe topology  相似文献   
40.
Phase-change read-and-write memory (PRAM) is a promising memory that can solve the problems of conventional memory—scalability, read/write speed, and reliability. We will review the opportunities and technical challenges of PRAM. The most important challenge of PRAM is the reduction of the writing current. Various approaches to reduce the writing current will be reviewed and the prospects of PRAM are discussed.  相似文献   
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