Microcavity distributed-feedback laser using dye-doped polymeric thin films

An organic microcavity laser, in which all the stacked polymer layers are doped with pyrromethene-567 dye, is presented. Singlemode laser oscillation at 568 nm was obtained that was located in the middle of the stopband. The lasing threshold was found to be 260 nJ/pulse, which corresponded to 300 muJ/cm² in the pulse energy density     

Wide-wavelength tunable lasers with 100 ghz fsr ring resonators

A widely tunable laser, consisting of a 100 GHz FSR triple-ring resonator and a semiconductor optical amplifier, is presented. The 100 GHz FSR ring resonator makes it possible to demonstrate 96 nm wavelength tuning with stable single-mode operation produced by a large threshold gain difference     

A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning

A 16 Mb embedded DRAM macro in a fully CMOS logic compatible 90 nm process with a low noise core architecture and a high-accuracy post-fabrication tuning scheme has been developed. Based on the proposed techniques, 61% improvement of the sensing accuracy is realized. Even with the smallest 5 fF/cell capacitance, a 322 MHz random-cycle access while 32 ms data retention time which contributes to save the data retention power down to 60 /spl mu/W are achieved.     

Sub-50-nm physical gate length CMOS technology and beyond usingsteep halo

Sub-50-nm CMOS devices are investigated using steep halo and shallow source/drain extensions. By using a high-ramp-rate spike annealing (HRR-SA) process and high-dose halo, 45-nm CMOS devices are fabricated with drive currents of 650 and 300 μA/μm for an off current of less than 10 nA/μm at 1.2 V with T_ox^inv =2.5 nm. For an off current less than 300 nA/μm, 33-nm pMOSFETs have a high drive current of 400 uA/μm. Short-channel effect and reverse short-channel effect are suppressed simultaneously by using the HRR-SA process to activate a source/drain extension (SDE) after forming a deep source/drain (S/D). This process sequence is defined as a reverse-order S/D (R-S/D) formation. By using this formation, 24-nm nMOSFETs are achieved with a high drive current of 800 μA/μm for an off current of less than 300 μA/μm at 1.2 V. This high drive current might be a result of a steep halo structure reducing the spreading resistance of source/drain extensions     

A 128-kb FeRAM macro for contact/contactless smart-card microcontrollers

This paper describes a 128-kb FeRAM macro for smart-card microcontrollers. This macro, which was designed and fabricated using a 0.35-/spl mu/m three-metal CMOS and a Capacitor-on-Metal/Via-stacked-Plug (CMVP) process technology, is ideally suited for recent system LSIs such as smart-card microcontrollers. It has a flexible memory size ranging from 32 to 128 kb, a low consumption current of 0.3 mA, and endurance of more than 10/sup 8/ write/read cycles under a wide range of supply voltages, from 2.7 to 5.5 V. These characteristics, which are required of not only contact-type smart-card microcontrollers but also contactless-type ones, were achieved by using four newly developed circuit technologies: 1) a three-metal CMVP memory cell; 2) a voltage-regulating architecture; 3) a main/sub bitline and wordline structure; and 4) a dynamic-type offset sense amplifier.     

LD抽运的Cr4+∶YAG被动调Q Nd∶YAG激光器

研究了不同谐振腔下不同透射率的Cr4 + ∶YAG调Q的激光输出特性。采用透射率为 82 %的Cr4 + ∶YAG ,在抽运功率 1 1W时 ,激光重复频率小于 3kHz,单脉冲能量达 2 0 μJ ,可以作为微脉冲激光雷达的发射光源。分析和比较了实验结果和理论计算 ,两者吻合较好     

Sub-50 nm P-channel FinFET

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an I_dsat of 820 μA/μm at V_ds=V_gs=1.2 V and T _ox=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm     

A 76-mm2 8-Mb chain ferroelectric memory

This paper demonstrates the first 8-Mb chain ferroelectric RAM (chain FeRAM) with 0,25-μm 2-metal CMOS technology. A small die of 76 mm² and a high average cell/chip area efficiency of 57.4 % have been realized by introducing not only chain architecture but also four new techniques: 1) a one-pitch shift cell realizes small cell size of 5.2 μm²; 2) a new hierarchical wordline architecture reduces row-decoder and plate-driver areas without an extra metal layer; 3) a small-area dummy cell scheme reduces dummy capacitor size to 1/3 of the conventional one; and 4) a new array activation scheme reduces dataline and second amplifier areas. As a result, the chain architecture with these new techniques reduces die size to 65% of that of the conventional FeRAM. Moreover a ferroelectric capacitor overdrive scheme enables sufficient polarization switching, without overbias memory cell array. This scheme lowers the minimum operation voltage by 0.23 V, and enables 2.5-V V_dd operation. Thanks to fast cell plateline drive of chain architecture, the 8-Mb chain FeRAM has achieved the fastest random access time, 40 ns, and read/write cycle time, 70 ns, at 3.0 V so far reported     

Formation of uniform GaAs multi-atomic steps with 20–30 nm periodicity and related structures on vicinal (111)B planes by MBE

We studied morphology of GaAs surfaces and the transport properties of two-dimensional electron gas (2DEG) on vicinal (111)B planes. Multi-atomic steps (MASs) are found on the vicinal (111)B facet grown by molecular beam epitaxy, which will affect electron transport on the facet. We also studied how the morphology of GaAs epilayers on vicinal (111)B substrates depends on growth conditions, especially on the As₄ flux. The uniformity of MASs on the substrates have been improved and smooth surfaces were obtained when the GaAs was grown with high As₄ flux, providing step periodicity of 20 nm. The channel resistance of the 2DEG perpendicular to the MASs is reduced drastically with this smooth morphology. These findings are valuable not only for fabricating quantum devices on the (111)B facets but also those on the vicinal (111)B substrates.     

An experimental 1.5-V 64-Mb DRAM

Low-voltage circuit technologies for higher-density dynamic RAMs (DRAMs) and their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage are presented. A complementary current sensing scheme is proposed to reduce data transmission delay. A speed improvement of 20 ns was achieved when utilizing a 1.5-V power supply. An accurate and speed-enhanced half-V_CC voltage generator with a current-mirror amplifier and tri-state buffer is proposed. With it, a response time reduction of about 1.5 decades was realized. A word-line driver with a charge-pump circuit was developed to achieve a high boost ratio. A ratio of about 1.8 was obtained from a power supply voltage as low as 1.0 V. A 1.28 μm² crown-shaped stacked-capacitor (CROWN) cell was also made to ensure a sufficient storage charge and to minimize data-line interference noise. An experimental 1.5 V 64 Mb DRAM was designed and fabricated with these technologies and 0.3 μm electron-beam lithography. A typical access time of 70 ns was obtained, and a further reduction of 50 ns is expected based on simulation results. Thus, a high-speed performance, comparable to that of 16-Mb DRAMs, can be achieved with a typical power dissipation of 44 mW, one tenth that of 16-Mb DRAMs. This indicates that a low-voltage battery operation is a promising target for future DRAMs