Computing the Average Symbol Error Probability of the MPSK System Having Quadrature Error

When quadrature error exists, the shape of the M‐ary phase shift keying (MPSK) signal constellation becomes skewed‐elliptic. Each MPSK symbol takes on a different symbol error probability (SEP) value. The analytical results presented thus far have been derived from studies which examined the SEP problem assuming that the SEP of each MPSK symbol is equally likely; therefore, those results should not be treated as offering a complete solution. In this letter, we present a new and more complete solution to the SEP problem of MPSK by relaxing the above assumption and finding the expressions for the average as well as individual SEP in the presence of quadrature error.     

Shared hardware,high throughput implementation of 2D 4 × 4 and 8 × 8 integer transform for H.264/AVC high-profile coders

Two-dimensional discrete cosine transforms are used in the core transformations in all profiles of the H.264/Advanced video coding (AVC) standard. In this paper, implementing the resource sharing of high throughput 4 × 4 and 8 × 8 forward and inverse integer transforms for high definition H.264 is presented. It is shown that the 4 × 4 forward/inverse transform can be obtained from 8 × 8 forward/inverse transform using selective data input and data arrangement at intermediate stages. Fast 8 × 8 forward and inverse transform is implemented using matrix decomposition and matrix operation such as Kronecker product and direct sum. The proposed implementation does not require any transpose memory and has a dual clocked pipeline structure. Compared with existing designs, the gate count is reduced by 27.7% in the proposed design. The maximum operating frequency of the proposed system is approx. 1.3 GHz, while the throughput is 7 G and 18.7 G pixels/s for 4 × 4 and 8 × 8 forward integer transforms, respectively. The proposed design can be used for real time H.264/AVC high definition processing owing to its high throughput and low hardware cost.     

Multiple feedback algorithm for RFID MAC protocols

This letter introduces a new tree-based anti-collision scheme using multiple feedbacks for uplink tag random access in a single-cell scenario. We examine MAC efficiency improvements that result from the proposed scheme in terms of uplink (UL) throughput for emerging radio frequency identification (RFID) networks, and compare it with the conventional tree based RFID MAC in ISO 18000-6 Type B standard.     

Mucoadhesive Phenolic Pectin Hydrogels for Saliva Substitute and Oral Patch

Oral disease is one of the most common conditions worldwide, negatively affecting general health, reducing the quality of life, and often developing into systemic illness. However, the design of therapeutic agents for oral diseases is challenging due to various unique features of the oral cavity, including its wet and dynamic environment and curved shape. Herein, the development of highly biocompatible mucoadhesive functional hydrogels for oral applications is reported, generated by introducing bio-inspired phenolic moieties into a pectin polymer. Pyrogallol-functionalized pectin (Pec-PG) can be crosslinked in situ via autoxidation without chemical agents and readily fabricated as various formulations. Sprayable Pec-PG hydrogel exhibits strong mucoadhesion and outstanding hydration ability ex vivo and in vivo, thus displaying significant potential as a novel saliva substitute for dry mouth. The authors further show that topical application of mucoadhesive Pec-PG patches pre-loaded with corticosteroid significantly promotes the repair of diabetic oral ulcer tissue via prolonged drug release, free radical scavenging, and physical barrier effects. Moreover, similar applications for oral ulcer treatment using a pectin hydrogel modified with catechol (Pec-CA), another phenolic moiety are demonstrated. Together, these findings suggest that mucoadhesive phenolic pectin derivatives can provide highly biocompatible, convenient, and effective hydrogel platforms for treating oral diseases.     

Variable VCC design techniques forbattery-operated DRAMs

Wide-voltage-range DRAMs with extended data retention are desirable for battery-operated or portable computers and consumer devices. The techniques required to obtain wide operation, functionality, and performance of standard DRAMs from 1.8 V (two NiCd or alkaline batteries) to 3.6 V (upper end of LVTTL standard) are described. Specific techniques shown are: (1) a low-power and low-voltage reference generator for detecting V_CC level; (2) compensation of DC generators, V_BB and V_PP, for obtaining high speed at reduced voltages; (3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and (4) a programmable V_CC variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16 M DRAM (2 M×8) by simulation     

Scale and rotation invariant pattern recognition using complex-log mapping and augmented second order neural network

A scale and rotation invariant pattern recognition system using complex-log mapping (CLM) and an augmented second order neural network (SONN) is proposed. CLM is very useful for extracting the scale and rotation invariant features. The results are, however, given in a wrap-around translated form. This problem is solved with an augmented SONN. Experimental results show that the proposed system has improved recognition performance.<>     

An accurate intrinsic capacitance modeling for deep submicrometerMOSFET's

This paper presents a new approach to the modeling of MOSFET capacitive characteristics for accurate simulation of deep submicrometer integrated circuits. The C-V characteristics of our new quasistatic intrinsic capacitance model accurately describes the short channel effects of deep submicrometer MOSFET's by accounting for velocity saturation and series resistance effects. The use of charge equations consistent with the short channel I-V characteristics leads to C-V characteristics which preserve all major short channel effects. The C-V calculation, based on nonpinned surface potential approach and drift-diffusion model, shows highly accurate short-channel effects and inherently smooth transitions for all conditions of device operation. The accuracy of the C-V characteristics has been demonstrated by comparison with the Ward-Dutton model and PISCES simulation results     

Temperature-compensation circuit techniques for high-density CMOSDRAMs

Temperature-compensation circuit techniques are presented for the CMOS DRAM internal voltage converter, the RC-delay circuit, and the back-bias generator, which do not need any additional process steps. The above-mentioned circuits have been designed and evaluated through a 16-Mb CMOS DRAM process. These circuits have shown an internal voltage converter (IVC) with an internal voltage temperature coefficient of 185 ppm/°C, and an RC-delay circuit with a delay time temperature coefficient of 0.03%/°C. As a result, a 6.5-ns faster RAS access time and improved latchup immunity have been achieved, compared with conventional circuit techniques     

A digital technique to estimate second-order distortion usinghigher order coherence spectra

A digital spectral method for evaluating second-order distortion of a nonlinear system, which can be represented by Volterra kernels up to second order and which is subjected to a random noise input, is discussed. The importance of departures from the commonly assumed Gaussian excitation is investigated. The Hinich test is shown to be an appropriate test for orthogonality in the system identification. Tests for Gaussianity of two important sources, which are commonly used for Gaussian inputs in nonlinear system identification, are presented: (1) commercial software routines for simulation experiments, and (2) noise generators for practical experiments. The deleterious effects of assuming a Gaussian input when it is not are demonstrated. The random input method for evaluating the second-order distortion of a nonlinear system is compared with the sine-wave input method using both simulation and experimental data. The approach is applied to a loudspeaker in the low-frequency band     

A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using aNAND flash memory technology

A 3.3-V 16-Mb nonvolatile memory having operation virtually identical to DRAM with package pin compatibility has been developed. Read and write operations are fully DRAM compatible except for a longer RAS precharge time after write. Fast random access time of 63 ns with the NAND flash memory cell is achieved by using a hierarchical row decoder scheme and a unique folded bit-line architecture which also allows bit-by-bit program verify and inhibit operation. Fast page mode with a column address access time of 21 ns is achieved by sensing and latching 4 k cells simultaneously. To allow byte alterability, nonvolatile restore operation with self-contained erase is developed. Self-contained erase is word-line based, and increased cell disturb due to the word-line based erase is relaxed by adding a boosted bit-line scheme to a conventional self-boosting technique. The device is fabricated in a 0.5-μm triple-well, p-substrate CMOS process using two-metal and three-poly interconnect layers. A resulting die size is 86.6 mm², and the effective cell size including the overhead of string select transistors is 2.0 μm²