High IIP3 and Low-Noise CMOS Mixer Using Non-linear Feedback Technique

A third-order intermodulation cancelation technique using a non-linear feedback is proposed to design a low-power low-distortion mixer in a 65 nm standard CMOS technology. The IM3 cancelation is achieved by estimating distorting error at a non-linear feedback element and subtracting it from the input. The linearization technique is utilized in the input trans-conductance of the mixer. The circuit functionality is analyzed using Volterra series. The covering frequency range of the mixer is 800 MHz to 5 GHz. The technique increases the input-referred third-order intercept point (IIP3) and input 1 dB compression point to +16.4 dBm and −1.87 dBm, respectively. It obtains a gain of 9 dB and an input-referred noise of 1.84 nV/?{}/\sqrt{}Hz while consumes 8.75 mA from 1.2 V supply. The layout of the mixer occupies 0.315 mm × 0.296 mm of silicon area.     

Dependability analysis for characterizing Google cluster reliability

Cloud solutions are emerging as a new suitable way of transforming traditional IT data centers to highly available and reliable computing resources for hosting critical applications and data. However, software and hardware failures are a common problem in cloud datacenters that can lead to harmful damages. In this paper, we analyze the physical server failures in the Google cloud datacenter. We study the Google cluster properties to investigate the relationship among physical servers' failure rate and jobs failure events. The failure rate of Google cluster executed jobs and servers is taken into consideration during a 29‐day period. We present a reliability model for Google cluster physical machines using the continuous time Markov chains according to this observation. We attempt to analyze the obtained model through SHARPE software packages to improve the understanding of failure events in the Google cloud cluster. We also explore the cluster availability based on parameters like steady‐state availability, steady‐state unavailability, mean time to failure, and mean time to repair in the Google cluster.     

A dynamic search pattern motion estimation algorithm using prioritized motion vectors

Motion estimation is one of the critical parts in video compression standards with a high computational load. Many motion estimation algorithms have been developed to reduce the number of search points compared to a full-search algorithm without losing the quality considerably. Most of them use fixed search patterns in their first step which may suffer from trapping into local minima or searching unnecessary blocks due to inappropriate size and type of search patterns. In this paper, a new dynamic search pattern using motion vectors of spatial and temporal neighboring blocks is proposed. The motion vectors of neighboring blocks are prioritized, in order to efficiently use of halfway stop technique. The simulation results indicate that proposed algorithm is very close to the full-search algorithm in quality, compared to other rivals. Moreover, the average number of searches is often less than other algorithms.     

Advanced Bioresponsive Multitasking Hydrogels in the New Era of Biomedicine

Advanced forms of hydrogels have many inherently desirable properties and can be designed with different structures and functions. In particular, bioresponsive multifunctional hydrogels can carry out sophisticated biological functions. These include in situ single-cell approaches, capturing, analysis, and release of living cells, biomimetics of cell, tissue, and tumor-specific niches. They can allow in vivo cell manipulation and act as novel drug delivery systems, allowing diagnostic, therapeutic, vaccination, and immunotherapy methods. In the present review of multitasking hydrogels, new approaches and devices classified into point-of-care testing (POCT), microarrays, single-cell/rare cell approaches, artificial membranes, biomimetic modeling systems, nanodoctors, and microneedle patches are summarized. The potentials and application of each format are critically discussed, and some limitations are highlighted. Finally, how hydrogels can enable an “all-in-one platform” to play a key role in cancer therapy, regenerative medicine, and the treatment of inflammatory, degenerative, genetic, and metabolic diseases is being looked forward to.     

Decimal SRT Square Root: Algorithm and Architecture

Given the popularity of decimal arithmetic, hardware implementation of decimal operations has been a hot topic of research in recent decades. Besides the four basic operations, the square root can be implemented as an instruction directly in the hardware, which improves the performance of the decimal floating-point unit in the processors. Hardware implementation of decimal square rooters is usually done using either functional or digit-recurrence algorithms. Functional algorithms, entailing multiplication per iteration, seem inadequate to use for decimal square roots, given the high cost of decimal multipliers. On the other hand, digit-recurrence square root algorithms, particularly SRT (this method is named after its creators, Sweeney, Robertson, and Tocher) algorithms, are simple and well suited for decimal arithmetic. This paper, with the intention of reducing the latency of the decimal square root operation while maintaining a reasonable cost, proposes an SRT algorithm and the corresponding hardware architecture to compute the decimal square root. The proposed fixed-point square root design requires n+3 cycles to compute an n-digit root; the synthesis results show an area cost of about 31K NAND2 and a cycle time of 40 FO4. These results reveal the 14 % speed advantage of the proposed decimal square root architecture over the fastest previous work (which uses a functional algorithm) with about a quarter of the area.     

Transient detection in COTS processors using software approach

This paper presents a software-based error detection scheme called enhanced committed instructions counting (ECIC) for embedded and real-time systems using commercial off-the-shelf (COTS) processors. The scheme uses the internal performance monitoring features of a processor, which provides the ability to count the number of committed instructions in a program. To evaluate the ECIC scheme, 6000 software induced faults are injected into a 32-bit Pentium® processor. The results show that the error detection coverage varies between 90.52% and 98.18%, for different workloads.     

ADC Multi-Site Test Based on a Pre-test with Digital Input Stimulus

This paper describes two novel algorithms based on the time-modulo reconstruction method intended for detection of the parametric faults in analogue-to-digital converters (ADC). In both algorithms, a pulse signal, in its slightly adapted form to allow sufficient time for converter settling, is taken as the test stimulus relieving the burden placed on the accuracy requirement of the excitation source. Instead of calculating the accurate conventional dynamic and static parameters, a signature result is obtained through the analysis of the output data in the time domain. The basic concept of the algorithms is the evaluation on the performance of ADCs by the comparison of the similarity of the output waveforms. The multi-site test is expensive for traditional specification-based tests of ADCs, as high quality analogue data generators are required. Based on these two algorithms, this paper proposes a solution for this problem. The objective of the test scheme is not to completely replace traditional specification-based tests, but to provide a reliable method for early identification of excessive parameter variations in production test that allows quickly discarding of most of the faulty circuits before performing a conventional test. The efficiency of the methods is validated on an industrial 12-bit pipelined ADC both in simulations and in measurements.