Development of improved methods for type testing present day mediumvoltage circuit breakers for outdoor service

Type testing for fault currents for medium-voltage circuit breakers rated at 15 kV to 72.5 kV is addressed. The ANSI designation of a new class of definite-purpose circuit breakers capable of switching transformer secondary faults and the introduction of the requirement for short-line-fault tests for breakers rated 72.5 kV and below have increased the difficulty of performing type tests in a testing laboratory. It is concluded that synthetic testing using the parallel current injection circuit is described in ANSI C37.081 provides the best available method for proving these complex requirements for medium-voltage circuit breakers     

Comparison of smoothness evaluation devices for power cablecompounds

A variety of data from different devices has been generated on the smoothness of shield products, but no direct comparison of compound smoothness for the devices themselves has been made. The purpose of this study was to compare four different methods for evaluating the smoothness of power cable compounds. The methods compared include: image analysis, laser scanning, mechanical profilometry and photomicroscopy with visual rating. Extruded tape samples of conductor shields, filled insulations and strippable shields were evaluated     

A bidding decision index for construction contractors

Results from applying the model on a sample of contractors, the majority of whom were international and operating in Egypt, reinforces the credibility of the developed methodology, claim the authors.     

Dynamic programming implementation on array processor architectures

Dynamic Programming (DP) applies to many signal and image processing applications including boundary following, the Viterbi algorithm, dynamic time warping, etc. This paper presents an array processor implementation of generic dynamic programming. Our architecture is a SIMD array attached to a host computer. The processing element of the architecture is based on an ASIC design opting for maximum speed-up. By adopting a torus interconnection network, a dual buffer structure, and a multilevel pipeline, the performance of the DP chip is expected to reach the order of several GOPS. The paper discusses both the dedicated hardware design and the data flow control of the DP chip and the total array.This work was supported in part by the NATO, Scientific and Environmental Affairs Division, Collaborative Research Grant SA.5-2-05(CRG.960201)424/96/JARC-501.     

On Toroidal Azulenoids and Other Shapes of Fullerene Cage

The possibility of toroidal cages of carbon with repeating five and seven membered ring pairs (azulene units) upon their surfaces is briefly discussed. Some of the difficulties in recognising possible fullerene cage shapes are pointed out.     

Design, manufacture and evaluation of a scalable high-performanceneural system

The authors describe a scalable neural system, HyperNet, based on a probabilistic RAM-based architecture and using a custom VLSI IC. A system using five HyperNet VLSI ICs and capable of realising up to 10240 neurons has been designed, manufactured and demonstrated to have the potential to learn more than three orders of magnitude faster than simulations on current workstations     

Seismic response of structures with supplemental damping

This paper presents a review of supplemental damping devices used for the control of the seismic response of structures. The mechanical properties of these devices are discussed and considerations in the design of energy absorbing systems are presented.