Second harmonic generation from a ferroelectric film

We derive an expression for transmittivity (T_SHG) of second harmonic generation (SHG) signals from a ferroelectric (FE) film. Intensities of up and down fields in the medium are investigated in relation to T_SHG. The derivations are made based on undepletion of input fields and nonlinear wave equation derived from the Maxwell equations. We present two cases: film without mirrors and with partial mirrors. Expressions for the newly derived nonlinear susceptibility coefficients of SHG for real crystal symmetry [J. Opt. Soc. Am. B 19 (2002) 2007] are used to get more realistic results. Variations in T_SHG with respect to film thickness are illustrated.     

1/f noise in large-area Hg<Subscript>1−x</Subscript>Cd<Subscript>x</Subscript>Te photodiodes

The 1/f noise in photovoltaic (PV) molecular-beam epitaxy (MBE)-grown Hg_1−xCd_xTe double-layer planar heterostructure (DLPH) large-area detectors is a critical noise component with the potential to limit sensitivity of the cross-track infrared sounder (CrIS) instrument. Therefore, an understanding of the origins and mechanisms of noise currents in these PV detectors is of great importance. Excess low-frequency noise has been measured on a number of 1000-μm-diameter active-area detectors of varying “quality” (i.e., having a wide range of I-V characteristics at 78 K). The 1/f noise was measured as a function of cut-off wavelength under illuminated conditions. For short-wave infrared (SWIR) detectors at 98 K, minimal 1/f noise was measured when the total current was dominated by diffusion with white noise spectral density in the mid-10⁻¹⁵A/Hz^1/2 range. For SWIR detectors dominated by other than diffusion current, the ratio, α, of the noise current in unit bandwidth i_n(f = 1 Hz, V_d = −60 mV, and Δf = 1 Hz) to dark current I_d(V_d = −60 mV) was α_SW-d = i_n/I_d ∼ 1 × 10⁻³. The SWIR detectors measured at 0 mV under illuminated conditions had median α_SW-P = i_n/I_ph ∼ 7 × 10⁻⁶. For mid-wave infrared (MWIR) detectors, α_MW-d = i_n/I_d ∼ 2 × 10⁻⁴, due to tunneling current contributions to the 1/f noise. Measurements on forty-nine 1000-μm-diameter MWIR detectors under illuminated conditions at 98 K and −60 mV bias resulted in α_MW-P = i_n/I_ph = 4.16 ± 1.69 × 10⁻⁶. A significant point to note is that the photo-induced noise spectra are nearly identical at 0 mV and 100 mV reverse bias, with a noise-current-to-photocurrent ratio, α_MW-P, in the mid 10⁻⁶ range. For long-wave infrared (LWIR) detectors measured at 78 K, the ratio, α_LW-d = i_n/I_d ∼ 6 × 10⁻⁶, for the best performers. The majority of the LWIR detectors exhibited α_LW-d on the order of 2 × 10⁻⁵. The photo-induced 1/f noise had α_LW-P = i_n/I_ph ∼ 5 × 10⁻⁶. The value of the noise-current-to-dark-current ratio, α appears to increase with increasing bandgap. It is not clear if this is due to different current mechanisms impacting 1/f noise performance. Measurements on detectors of different bandgaps are needed at temperatures where diffusion current is the dominant current. Excess low-frequency noise measurements made as a function of detector reverse bias indicate 1/f noise may result primarily from the dominant current mechanism at each particular bias. The 1/f noise was not a direct function of the applied bias.     

Evaluation and optimization of package processing and design through solder joint profile prediction

Solder joints are generated using a variety of methods to provide both mechanical and electrical connection for applications such as flip-chip, wafer level packaging, fine pitch, ball-grid array, and chip scale packages. Solder joint shape prediction has been incorporated as a key tool to aid in process development, wafer level and package level design and development, assembly, and reliability enhancement. This work demonstrates the application of an analytical model and the Surface Evolver software in analyzing a variety of solder processing methods and package types. Bump and joint shape prediction was conducted for the design of wafer level bumping, flip-chip assembly, and wafer level packaging. The results from the prediction methodologies are validated with experimentally measured geometries at each level of design.     

Training and optimization of an artificial neural network controlling a hybrid power filter

A hybrid power compensator (HPC) consisting of a static VAr compensator and a dynamic compensator needs to be optimally controlled during the compensation of nonlinear loads. The HPC must be controlled to meet minimum requirements in terms of power factor and harmonic distortion, while at the same time minimizing its total cost. An artificial neural network (ANN) is used to control the HPC amidst a very dynamic power system environment. The performance of a reference ANN is evaluated while controlling an HPC connected to a typical nonlinear industrial load. The training and performance of the ANN is then optimized in terms of training set size, training set packing and ANN topology and the performance compared to the reference ANN. This paper highlights the importance of optimising the mentioned ANN parameters to achieve optimum ANN training and modeling accuracy. The results obtained reveals that the application of an ANN in controlling an HPC is feasible given that the ANN parameters are chosen appropriately.     

Analytic models for the latency and steady-state throughput of TCP Tahoe, Reno, and SACK

Continuing the process of improvements made to TCP through the addition of new algorithms in Tahoe and Reno, TCP SACK aims to provide robustness to TCP in the presence of multiple losses from the same window. In this paper we present analytic models to estimate the latency and steady-state throughput of TCP Tahoe, Reno, and SACK and validate our models using both simulations and TCP traces collected from the Internet. In addition to being the first models for the latency of finite Tahoe and SACK flows, our model for the latency of TCP Reno gives a more accurate estimation of the transfer times than existing models. The improved accuracy is partly due to a more accurate modeling of the timeouts, evolution of cwnd during slow start and the delayed ACK timer. Our models also show that, under the losses introduced by the droptail queues which dominate most routers in the Internet, current implementations of SACK can fail to provide adequate protection against timeouts and a loss of roughly more than half the packets in a round will lead to timeouts. We also show that with independent losses SACK performs better than Tahoe and Reno and, as losses become correlated, Tahoe can outperform both Reno and SACK.     

Synthesis of ZSM‐5 Films and Monoliths with Bimodal Micro/Mesoscopic Structures

A route to synthesize ZSM‐5 crystals with a bimodal micro/mesoscopic pore system has been developed in this study; the successful incorporation of the mesopores within the ZSM‐5 structure was performed using tetrapropylammonium hydroxide (TPAOH)‐impregnated mesoporous materials containing carbon nanotubes in the pores, which were encapsulated in the ZSM‐5 crystals during a solid rearrangement process within the framework. Such mesoporous ZSM‐5 zeolites can be readily obtained as powders, thin films, or monoliths.     

The First Template‐Free Growth of Crystalline Silicon Microtubes

A simple template‐free high‐temperature evaporation method was developed for the growth of crystalline Si microtubes for the first time. As‐grown Si microtubes were characterized using X‐ray diffraction, scanning electron microscopy, transmission electron microscopy, and room‐temperature photoluminescence. The lengths of the Si tubes can reach several hundreds of micrometers; some of them have lengths on the order of millimeters. Each tube has a uniform outer diameter along its entire length, and the typical outer diameter is ≈ 2–3 μm. Most of the tubes have a wall thickness of ≈ 400–500 nm, though a considerable number of them exhibit a very thin wall thickness of ≈ 50 nm. Room‐temperature photoluminescence measurement shows the as‐synthesized Si microtubes have two strong emission peaks centered at ≈ 589 nm and ≈ 617 nm and a weak emission peak centered at ≈ 455 nm. A possible mechanism for the formation of these Si tubes is proposed. We believe that the present discovery of the crystalline Si microtubes will promote further experimental studies on their physical properties and smart applications.     

Optimal pilot waveform assisted modulation for ultrawideband communications

Ultrawideband (UWB) transmissions induce pronounced frequency-selective fading effects in their multipath propagation. Multipath diversity gains can be collected to enhance performance, provided that the underlying channel can be estimated at the receiver. To this end, we develop a novel pilot waveform assisted modulation (PWAM) scheme that is tailored for UWB communications. We select our PWAM parameters by jointly optimizing channel estimation performance and information rate. The resulting transmitter design maximizes the average capacity, which is shown to be equivalent to minimizing the mean-square channel estimation error, and thereby achieves the Crame/spl acute/r-Rao lower bound. Application of PWAM to practical UWB systems is promising because it entails simple integrate-and-dump operations at the frame rate. Equally important, it offers a flexible UWB channel estimator, capable of striking desirable rate-performance tradeoffs depending on the channel coherence time.     

Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).     

Static energy reduction techniques for microprocessor caches

Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of static energy consumption due to subthreshold leakage current in cache memory arrays. This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches. One technique employs low-leakage transistors in the memory cell. Another technique, power supply switching, can be used to turn off memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places memory cells in a standby state that preserves cell contents. In our experiments, we explore the energy and performance tradeoffs of these techniques. We also investigate the sensitivity of microprocessor performance and energy consumption to additional cache latency caused by leakage-reduction techniques.