Low Power Encoding Techniques for Dynamically Reconfigurable Hardware

In this paper, an approach to the implementation of digital systems is presented which utilizes dynamic hardware reconfiguration in order to automatically minimize the power dissipated on module interconnections such as system buses during system run time. Reduction of power dissipation is achieved by means of an activity-reducing system bus encoding technique. Encoder and decoder are implemented with dynamically reconfigured code tables which contain a transition minimizing code that is periodically recomputed during run time of the system in order to adapt to variations in the statistical parameters of the encoded data stream. We present the theoretical basics and an efficient implementation of a corresponding coder-decoder system. Experimental results showed a reduction in bus transition activity of up to 41%.     

Infrastructure Federation Through Virtualized Delegation of Resources and Services

Infrastructure federation is becoming an increasingly important issue for modern Distributed Computing Infrastructures (DCIs): Dynamic elasticity of quasi-static Grid environments, incorporation of special-purpose resources into commoditized Cloud infrastructures, cross-community collaboration for increasingly diverging areas of modern e-Science, and Cloud Bursting pose major challenges on the technical level for many resource and middleware providers. Especially with respect to increasing costs of operating data centers, the intelligent yet automated and secure sharing of resources is a key factor for success. With the D-Grid Scheduler Interoperability (DGSI) project within the German D-Grid Initiative, we provide a strategic technology for the automatically negotiated, SLA-secured, dynamically provisioned federation of resources and services for Grid-and Cloud-type infrastructures. This goal is achieved by complementing current DCI schedulers with the ability to federate infrastructure for the temporary leasing of resources and rechanneling of workloads. In this work, we describe the overall architecture and SLA-secured negotiation protocols within DGSI and depict an advanced mechanism for resource delegation through means of dynamically provisioned, virtualized middleware. Through this methodology, we provide the technological foundation for intelligent capacity planning and workload management in a cross-infrastructure fashion.     

Plate tectonic reconstructions with continuously closing plates

We present a new algorithm for modeling a self-consistent set of global plate polygons. Each plate polygon is composed of a finite list of plate margins, all with different Euler poles. We introduce a "continuously closed plate" (CCP), such that, as each margin moves independently, the plate polygon remains closed geometrically as a function of time. This method solves emerging needs in computational geodynamics to combine kinematic with dynamic models. Because they have polygons that are too widely spaced in time and have inconsistent motions between margins and plates, traditional global plate tectonic reconstructions have become inadequate for geodynamics. The CCP algorithm has been incorporated into the GPlates open-source paleogeographic system. The algorithm is a set of procedures and data structures that operate on collections of reconstructed geometric data to form closed plate polygons; the main data structures used for each plate polygon are based on a nested hierarchy of topological elements. Reconstructions with CCPs can be created, edited, visualized, and exported with GPlates. The native storage of the dynamic reconstructions is the GPlates Markup Language, GPML, which uses an XML-based file format called GML. We demonstrate the utility of the CCP method by creating a global reconstruction with continuously closing plates from 140 Ma to the present using data from existing, traditional reconstructions.     

Digit Pipelined Arithmetic for 3-D Massively Parallel Optoelectronic Circuits

A concept for a future integer arithmetic unit suitable for a realization with 3-D optoelectronic very large scale integrated (VLSI) circuits is presented. Due to the use of optical interconnections running vertically to the circuit's surface no pin limitation is given. This allows massively parallelism and a higher throughput performance than in all-electronic solutions. To exploit the potential of optical interconnections in VLSI systems efficiently well-adapted low-level algorithms and architectures have to be developed. This is demonstrated for a pipelined arithmetic unit using a redundant number representation. A transistor layout for the optoelectronic circuits is given as well as a specification for the necessary optical interconnection scheme linking the circuits with free-space optics. It is shown that the throughput can be increased by a factor of 10 to 50 compared to current all-electronic processors by considering state-of-the-art optical and optoelectronic technology. Furthermore we present results we gained by investigations on a first realized optoelectronic VLSI test chip.     

An extended analysis of memory hierarchies for efficient implementations of image processing applications

Through continued miniaturization of electronic devices embedded smart cameras are steadily becoming more and more important. The reduction of the camera size increases the spectrum of applications. In industrial applications the range of smart cameras spans from quality monitoring and position tracking to the calibration of production machines. In non-professional applications a distinct boom in action cameras combined with fused sensor information can be observed. However, all of these applications have a common bottleneck: the memory architecture. Most image processing applications are memory-bound tasks. Thus, the amount of time for transferring data with image processing applications decisively affects the application’s entire processing time. Different memory access patterns require different memory configurations and hierarchies. An insufficient match between the image processing application and the memory architecture leads to a poor performance in the image processing system. This can lead to longer processing times, and larger energy consumption rates. This work introduces new methods of classifying image processing applications by using their memory access pattern for mapping on memory architectures. Our work combines a simulation framework the heterogenous memory simulator with a analytical framework the memory analyzer to find bottlenecks inside the image processing application and aids in finding a suitable, application-specific memory configuration in terms of processing time and energy consumption.     

Anomalies in ontologies with rules

For the development of practical semantic applications, ontologies are commonly used with rule extensions. Prominent examples of semantic applications not only are Semantic Wikis, Semantic Desktops, but also advanced Web Services and agents. The application of rules increases the expressiveness of the underlying knowledge in many ways. Likewise, the integration not only creates new challenges for the design process of such ontologies, but also existing evaluation methods have to cope with the extension of ontologies by rules.Since the verification of Owl ontologies with rule extensions is not tractable in general, we propose to verify ontologies at the symbolic level by using a declarative approach: With the new language Datalog^?, known anomalies can be easily specified and tested in a compact manner. We introduce supplements to existing verification techniques to support the design of ontologies with rule enhancements, and we focus on the detection of anomalies that especially occur due to the combined use of rules and ontological definitions.