Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).     

On the physical and logical topology design of large-scale optical networks

We consider the problem of designing a network of optical cross-connects (OXCs) to provide end-to-end lightpath services to large numbers of label switched routers (LSRs). We present a set of heuristic algorithms to address the combined problem of physical topology design (i.e., determine the number of OXCs required and the fiber links among them) and logical topology design (i.e., determine the routing and wavelength assignment for the lightpaths among the LSRs). Unlike previous studies which were limited to small topologies with a handful of nodes and a few tens of lightpaths, we have applied our algorithms to networks with hundreds or thousands of LSRs and with a number of lightpaths that is an order of magnitude larger than the number of LSRs. In order to characterize the performance of our algorithms, we have developed lower bounds which can be computed efficiently. We present numerical results for up to 1000 LSRs and for a wide range of system parameters such as the number of wavelengths per fiber, the number of transceivers per LSR, and the number of ports per OXC. The results indicate that it is possible to build large-scale optical networks with rich connectivity in a cost-effective manner, using relatively few but properly dimensioned OXCs.     

Static energy reduction techniques for microprocessor caches

Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of static energy consumption due to subthreshold leakage current in cache memory arrays. This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches. One technique employs low-leakage transistors in the memory cell. Another technique, power supply switching, can be used to turn off memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places memory cells in a standby state that preserves cell contents. In our experiments, we explore the energy and performance tradeoffs of these techniques. We also investigate the sensitivity of microprocessor performance and energy consumption to additional cache latency caused by leakage-reduction techniques.     

An improved statistical analysis of the least mean fourth (LMF) adaptive algorithm

The paper presents an improved statistical analysis of the least mean fourth (LMF) adaptive algorithm behavior for a stationary Gaussian input. The analysis improves previous results in that higher order moments of the weight error vector are not neglected and that it is not restricted to a specific noise distribution. The analysis is based on the independence theory and assumes reasonably slow learning and a large number of adaptive filter coefficients. A new analytical model is derived, which is able to predict the algorithm behavior accurately, both during transient and in steady-state, for small step sizes and long impulse responses. The new model is valid for any zero-mean symmetric noise density function and for any signal-to-noise ratio (SNR). Computer simulations illustrate the accuracy of the new model in predicting the algorithm behavior in several different situations.     

2-D symmetry: theory and filter design applications

In this comprehensive review article, we present the theory of symmetry in two-dimensional (2-D) filter functions and in 2-D Fourier transforms. It is shown that when a filter frequency response possesses symmetry, the realization problem becomes relatively simple. Further, when the frequency response has no symmetry, there is a technique to decompose that frequency response into components each of which has the desired symmetry. This again reduces the complexity of two-dimensional filter design. A number of filter design examples are illustrated.     

High-performance MIM capacitor using ALD high-k HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectrics

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.     

Hydrogen annealing effect on DC and low-frequency noise characteristics in CMOS FinFETs

The hydrogen annealing process has been used to improve surface roughness of the Si-fin in CMOS FinFETs for the first time. Hydrogen annealing was performed after Si-fin etch and before gate oxidation. As a result, increased saturation current with a lowered threshold voltage and a decreased low-frequency noise level over the entire range of drain current have been attained. The low-frequency noise characteristics indicate that the oxide trap density is reduced by a factor of 3 due to annealing. These results suggest that hydrogen annealing is very effective for improving device performance and for attaining a high-quality surface of the etched Si-fin.     

Effect of anisotropy of tin on thermomechanical behavior of solder joints

Properties of body centered tetragonal tin are highly anisotropic. As a consequence large stresses can develop at the tin grain boundaries due to coefficient of thermal expansion mismatch during temperature excursions. A modeling approach to evaluate the 3D stress states that develop at grain boundaries during thermomechanical fatigue in tin-based solder is presented. Development of significant amounts of stresses in the plane of the grain boundary can cause grain-boundary sliding and surface-relief effects, while those normal to the grain boundary can cause grain-boundary decohesion and cracking.