无线网络融合的安全技术研究

融合多种网络可满足用户长日寸间连接和尽可能获得较高数据传输速率的需要，但融合后的网络也将各种网络的安全缺陷带进融合网络中。这不但给融合网络的运行带进各种原有的安全问题，而且增加了一些新的安全问题。对此，文章提出了基于恢复的多重防护解决方案，并使用公钥加密算法鉴权。使用私钥对通信数据进行加密。该方案可以为系统提供可靠的安全性，并实现用户对服务的不可抵赖性。该方案还处于研究起步阶段，下一步还需要明确各层的正确行为，以及出现多个恶意节点对某个合法节点诬陷时所应采取的行动。     

陆东凹陷油气藏烃类组成非均质性及其意义

陆东凹陷原油和油砂抽提物中烃类的宏观组成存在着明显的非均质性。在高孔隙度(>15%)储层单元中,饱和烃的含量高,占总组成的含量均大于40%,而极性化合物则相对较低,一般不足40%;相反,在低孔隙度(<15%)储层单元中,饱和烃的含量明显降低,而极性化合物则显著增加。此外,陆东凹陷原油和油砂抽提物中烃类成熟度亦存在着非均质性:在高孔隙度储层中,原油和油砂烃类的成熟度参数高,而在低孔隙度储层中原油和油砂烃类的成熟度参数低。根据原油和油砂抽提物中烃类的宏观组成特征和成熟度参数的变化规律,提出了陆东凹陷油气聚集模式。     

Synthesis of ZSM‐5 Films and Monoliths with Bimodal Micro/Mesoscopic Structures

A route to synthesize ZSM‐5 crystals with a bimodal micro/mesoscopic pore system has been developed in this study; the successful incorporation of the mesopores within the ZSM‐5 structure was performed using tetrapropylammonium hydroxide (TPAOH)‐impregnated mesoporous materials containing carbon nanotubes in the pores, which were encapsulated in the ZSM‐5 crystals during a solid rearrangement process within the framework. Such mesoporous ZSM‐5 zeolites can be readily obtained as powders, thin films, or monoliths.     

Passive alignment method of polymer PLC devices by using a hot embossing technique

A novel fabrication process using a hot embossing technique has been developed for micromechanical passive alignment of polymer planar lightwave circuit (PLC) devices. With only one step of embossing, single-mode waveguide straight channels and micropedestals for passive aligning are simultaneously defined on a polymer thin film with an accuracy of /spl plusmn/0.5 /spl mu/m. This process reduces the steps for fabricating alignment structures. A fabricated polymer PLC chip and fibers are combined on a v-grooved silicon optical bench (SiOB) in a flip-chip manner. The process provides a coupling loss as low as 0.67 dB per coupling face and a cost-effective packaging solution for various polymer PLC devices.     

Scaling planar silicon devices

The generation-over-generation scaling of critical CMOS technology parameters is ultimately bound by nonscalable limitations, such as the thermal voltage and the elementary electronic charge. Sustained improvement in performance and density has required the introduction of new device structures and materials. Partially depleted SOI, a most recent MOSFET innovation, has extended VLSI performance while introducing unique idiosyncrasies. Fully depleted SOI is one logical extension of this device design direction. Gate dielectric tunneling, device self-heating, and single-event upsets present developers of these next-generation devices with new challenges. Strained silicon and high-permittivity gate dielectric are examples of new materials that will enable CMOS developers to continue to deliver device performance enhancements in the sub-100 nm regime.     

Effects of SiN passivation and high-electric field on AlGaN-GaN HFET degradation

The authors report on the effects of silicon nitride (SiN) surface passivation and high-electric field stress (hot electron stress) on the degradation of undoped AlGaN-GaN power HFETs. Stressed devices demonstrated a decrease in the drain current and maximum transconductance and an increase in the parasitic drain series resistance, gate leakage, and subthreshold current. The unpassivated devices showed more significant degradation than SiN passivated devices. Gate lag phenomenon was observed from unpassivated devices and removed by SiN passivation. However, SiN passivated devices also showed gate lag phenomena after high-electric field stress, which suggests possible changes in surface trap profiles occurred during high-electric field stress test.     

High-performance MIM capacitor using ALD high-k HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectrics

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.     

三网互联的几个关键技术

对三网互联的几个关键技术进行分析与研究，介绍利用IP技术解决有线电视网地址选择问题，探讨怎样将ATM技术与IP技术相互融合，使真正的信息高速公路成为现实，阐述利用H．323标准全面解决视频网络方案。     

Throughput analysis for multicast switches with multiple input queues

This letter analyzes the saturated throughput for multicast switches with multiple input queues per input port. Under the assumptions of a Poisson uniform traffic model and random packet scheduling policy, we derive the multicast switch saturated throughput under different fanouts. To verify the analysis, extensive simulations are conducted with different switch sizes and fanouts. It is shown that the theoretical analysis and the simulation results have a discrepancy less than 1.9%. Results from this letter can be used as a guidance to design the optimal queuing for multicast switches.     

基于SOI的双极场效应晶体管

在分析了双极型晶体管和场效应晶体管各自的特点和不足后，介绍了一种既具有双极型晶体管较大电流容量和功率输出，又具有场效应晶体管高输入阻抗的电子器件——双极MOS场效应晶体管(BJMOSFET)，同时指出体硅BJMOSFET的阳极扩散区与衬底之间存在较大的漏电流，可产生较大的寄生效应。提出了一种新型固体电子器件——基于SOI的BJMOSFET，分析了其工作原理j与体硅BJMOSFET比较，由于SOI技术完整的介质隔离避免了体硅器件中存在的大部分寄生效应，使基于SOI的BJMOSFET在体效应、热载流子效应、寄生电容、短沟道效应和闩锁效应等方面具有更优良的特性。