微机械槽板结构空气压膜阻尼的修正雷诺方程

推导出了一个适用于槽板结构压膜空气阻尼的微分方程.该方程与传统雷诺方程的区别是在雷诺方程的左边增加了一个用以表示气体从槽流出所引起的阻尼效应的修正项,并考虑了槽中有限气流通道长度的端头修正.在适当的边界条件下,利用此方程可以求解槽板压膜阻尼的压强分布、阻尼力和阻尼力系数.该槽板结构压膜空气阻尼的微分方程对槽板的厚度和横向尺度没有限制,为分析有限尺寸和有限厚度槽板的压膜空气阻尼提供了一个有用的方法.     

一种新型半绝缘键合SOI结构

报道了一种新型半绝缘键合SOI结构,采用化学气相淀积加外延生长键合过渡多晶硅层的方法实现了该结构.研制出的这种新结构,完整率大于85%,Si-Si键合界面接触比电阻小于5×10-4Ω·cm2.这种新结构可以广泛用于高低压功率集成电路、高可靠集成电路、MEMS、硅基光电集成等新器件和电路中.     

两种自主开发的图形外延SiGe工艺

使用清华大学微电子学研究所研发的UHV/CVD系统深入研究了图形外延SiGe工艺,分别选用单一的SiO2介质层和SiO2/P0ly-Si复合介质层,作为图形外延SiGe单晶材料的窗口屏蔽介质,开发出了不同的实用化图形外延SiGe工艺.     

基于SOCKS V5/TLS协议的防火墙系统组成与设计

从综合运用多种安全技术与机制增强防火墙性能的思想出发,本文论述了在SOCKS VS 协议中实现TLS协议的防火墙系统的组成与设计,详细阐述了其软硬件环境,系统功能模块以及在Windows NT下的配置,图示了运行效果。     

Kernel-based deterministic annealing algorithm for data clustering

Data clustering in kernel-induced feature space is interesting in that, by nonlinearly mapping the observed data from a low-dimensional input space into a high (possibly infinite)-dimensional feature space by means of a given kernel function, the kernel-based clustering can reveal complicated (e.g. linearly nonseparable) data structures that may be missed by traditional clustering methods in the standard Euclidean space. A kernel-based deterministic annealing (KDA) algorithm is developed for data clustering by using a Gaussian kernel function. The Gaussian parameter (width), which determines the nonlinear mapping together with the Gaussian kernel, is adaptively selected by the scaled inverse of data covariance. The effectiveness of the Gaussian parameter (width) selection method and the superiority of the KDA algorithm for clustering a variety of data structures are supported by the experimental results on artificial and real data sets     

Nonlinear Transient and Distortion Analysis via Frequency Domain Volterra Series

This paper presents a novel approach for transient and distortion analyses for time-invariant and periodically time-varying mildly nonlinear analog circuits. Our method is based on a frequency domain Volterra series representation of nonlinear circuits. It computes the nonlinear responses using a nonlinear current method that recursively solves a series of linear Volterra circuits to obtain linear and higher-order responses of a nonlinear circuit. Unlike existing approaches, where Volterra circuits are solved mainly in the time domain, the new method solves the linear Volterra circuits directly in the frequency domain via an efficient graph-based technique, which can derive transfer functions for any large linear network efficiently. As a result, both frequency domain characteristics, like harmonic and intermodulation distortion, and time domain waveforms can be computed efficiently. The new algorithm takes advantage of identical Volterra circuits for second- and higher-order responses, which results in significant savings in driving the transfer functions. Experimental results for two circuits—a low-noise amplifier and a switching mixer—are obtained and compared with SPICE3 to validate the effectiveness of this method.     

On the complexity of and algorithms for finding the shortest path with a disjoint counterpart

Finding a disjoint path pair is an important component in survivable networks. Since the traffic is carried on the active (working) path most of the time, it is useful to find a disjoint path pair such that the length of the shorter path (to be used as the active path) is minimized. In this paper, we first address such a Min-Min problem. We prove that this problem is NP-complete in either single link cost (e.g., dedicated backup bandwidth) or dual link cost (e.g., shared backup bandwidth) networks. In addition, it is NP-hard to obtain a K-approximation to the optimal solution for any K>1. Our proof is extended to another open question regarding the computational complexity of a restricted version of the Min-Sum problem in an undirected network with ordered dual cost links (called the MSOD problem). To solve the Min-Min problem efficiently, we introduce a novel concept called conflicting link set which provides insights into the so-called trap problem, and develop a divide-and-conquer strategy. The result is an effective heuristic for the Min-Min problem called COnflicting Link Exclusion (COLE), which can outperform other approaches in terms of both the optimality and running time. We also apply COLE to the MSOD problem to efficiently provide shared path protection and conduct comprehensive performance evaluation as well as comparison of various schemes for shared path protection. We show that COLE not only processes connection requests much faster than existing integer linear programming (ILP)-based approaches but also achieves a good balance among the active path length, bandwidth efficiency, and recovery time.     

一种低压低功耗SRAM/SOI单元设计

提出一种改进4管自体偏压结构SRAM/SOI单元.基于TSUPREM4和MEDICI软件的模拟和结构性能的分析,设计单元结构并选取结构参数.该结构采用nMOS栅下的含p 埋沟的衬底体电阻代替传统6管CMOSSRAM单元中的pMOS元件,具有面积小、工艺简单的优点.该结构可以在0.5V的电源电压下正常工作,与6管单元相比,该单元瞬态响应正常,功耗只有6管单元的1/10,满足低压低功耗的要求.     

Injection-locked Fabry-Pe/spl acute/rot laser with electronic feedback for clock recovery from high-speed OTDM signals

We demonstrate the use of an injection-locked Fabry-Pe/spl acute/rot laser diode with electronic feedback for base-rate clock recovery in N/spl times/10 Gb/s optical time-division-multiplexing (OTDM) systems. Injection-locking enhances the resonance frequency of the laser and the electrical feedback achieves strong resonance at the base-rate frequency of the injected data streams, enabling ultrastable electrical clock signal generation at the base rate of 10 GHz. Experimental demonstrations for clock recovery at 10 GHz from 40-Gb/s OTDM data streams and 4-1 demultiplexing of the data using the extracted clock after fiber transmission is presented. The timing jitter measured in the recovered electrical clock is less than 0.25 ps.     

A self-timed divider using a new fast and robust pipeline scheme

This paper investigates the potential of self-timed property of differential cascode voltage switch logic (DCVSL) circuits, and examines architectural techniques for achieving self-timing in DCVSL circuits. As a result, a fast and robust handshake scheme for dynamic asynchronous circuit design is proposed. It is novel and more general than other similar schemes. The proposed self-timed datapath scheme is verified by an 8-bit divider which is implemented using AMS 0.6-μm CMOS technology, and the chip size is about 1.66 mm×1.70 mm. The chip testing results show that the divider functions correctly and the latency for 8-bit quotient-digit generation is 17 ns (about 58.8 MHz)