Sub‐5 nm Dendrimer Directed Self‐Assembly with Large‐Area Uniform Alignment by Graphoepitaxy

Directed self‐assembly (DSA) using soft materials is an important method for producing periodic nanostructures because it is a simple, cost‐effective process for fabricating high‐resolution patterns. Most of the previously reported DSA methods exploit the self‐assembly of block copolymers, which generates a wide range of nanostructures. In this study, cylinders obtained from supramolecular dendrimer films with a high resolution (<5 nm) exhibit planar ordering over a macroscopic area via guiding topographical templates with a high aspect ratio (>10) and high spatial resolution (≈20 nm) of guiding line patterns. Theoretical and experimental studies reveal that this property is related to geometrical anchoring on the meniscus region and physical surface anchoring on the sidewall. Furthermore, this DSA of dendrimer cylinders is demonstrated by the non‐regular geometry of the patterned template. The macroscopic planar alignment of the dendrimer nanostructure reveals an extremely small feature size (≈4.7 nm) on the wafer scale (>16 cm²). This study is expected to open avenues for the production of a large family of supramolecular dendrimers with different phases and feature dimensions oriented by the DSA approach.     

A 44-GHz monolithic waveguide plane-wave amplifier with improvedunit cell design [using pHEMTs]

A 44-GHz monolithic waveguide plane-wave amplifier (PWA) with improved unit cell design is presented in this paper. The unit cell is a two-stage direct-coupled design and satisfies size, bistability, and stability requirements of the waveguide PWA. The ultra-compact unit cell had a cell size of 0.8 mm², and showed a small-signal gain of 8 dB and an output power of 15 dBm at 44 GHz with a corresponding dc-to-RF efficiency of 10%. A monolithic waveguide PWA using these unit cells showed a “flange-to-flange” gain of 5 dB, an output power of 0.3 W, and an efficiency of 2% at 44 GHz     

Reversible energy recovery logic circuit without non-adiabaticenergy loss

The authors propose a reversible energy recovery logic (RERL) circuit for ultra-low-energy consumption, which consumes only adiabatic energy loss and leakage current loss by completely eliminating non-adiabatic energy loss. It is a dual-rail adiabatic circuit using the concept of reversible logic with a new eight-phase clocking scheme. Simulation results show that at low-speed operation, the RERL consumes much less energy than the complementary static CMOS circuit and other adiabatic logic circuits     

Interdiffusion behavior of Hg in HgTe/CdTe superlattices grown on Cd0.96Zn0.04 Te (211)B substrates by molecular beam epitaxy

Double-crystal x-ray rocking curve (DCRC) and secondary-ion mass-spectroscopy (SIMS) measurements have been performed to investigate the effect of rapid thermal annealing on the interdiffusion behavior of Hg in HgTe/CdTe superlattices grown on Cd_0.96Zn_0.04Te (211)B substrates by molecular beam epitaxy. The sharp satellite peaks of the DCRC measurements on a 100-period HgTe/CdTe (100Å/100Å) superlattice show a periodic arrangement of the superlattice with high-quality interfaces. The negative direction of the entropy change obtained from the diffusion coefficients as a function of the reciprocal of the temperature after RTA indicates that the Hg diffusion for the annealed HgTe/CdTe superlattice is caused by an interstitial mechanism. The Cd and the Hg concentration profiles near the annealed HgTe/CdTe superlattice interfaces, as measured by SIMS, show a nonlinear behavior for Hg, originating from the interstitial diffusion mechanism of the Hg composition. These results indicate that a nonlinear interdiffusion behavior is dominant for HgTe/CdTe superlattices annealed at 190°C and that the rectangular shape of HgTe/CdTe superlattices may change to a parabolic shape because of the intermixing of Hg and Cd due to the thermal treatment.     

Still image coding based on vector quantization and fractalapproximation

In this paper, we propose a coding algorithm for still images using vector quantization (VQ) and fractal approximation, in which low-frequency components of an input image are approximated by VQ, and its residual is coded by fractal mapping. The conventional fractal coding algorithms indirectly used the gray patterns of an original image with contraction mapping, whereas the proposed fractal coding method employs an approximated and then decimated image as a domain pool and uses its gray patterns. Thus, the proposed algorithm utilizes fractal approximation without the constraint of contraction mapping. For approximation of an original image, we employ the discrete cosine transform (DCT) rather than conventional polynomial-based transforms. In addition, for variable blocksize segmentation, we use the fractal dimension of a block that represents the roughness of the gray surface of a region. Computer simulations with several test images show that the proposed method shows better performance than the conventional fractal coding methods for encoding still pictures.     

Thermally robust Ta2O5 capacitor for the256-Mbit DRAM

The thermal degradation of the Ta₂ O₅ capacitor during BPSG reflow has been studied. The cause of deterioration of Ta₂O₅ with the TiN top electrode was found to be the oxidation of TiN. By placing a poly-Si layer between TiN and BPSG to suppress oxidation, the low leakage current level was maintained after BPSG reflow at 850°C. The Ta₂O₅ capacitor with the TiN/poly-Si top electrode was integrated into 256-Mbit DRAM cells and excellent leakage current characteristics were obtained     

Outstanding Low-Temperature Performance of Structure-Controlled Graphene Anode Based on Surface-Controlled Charge Storage Mechanism

The energy and power performance of lithium (Li)-ion batteries is significantly reduced at low-temperature conditions, which is mainly due to the slow diffusion of Li-ions in graphite anode. Here, it is demonstrated that the effective utilization of the surface-controlled charge storage mechanism through the transition from layered graphite to 3D crumpled graphene (CG) dramatically improves the Li-ion charge storage kinetics and structural stability at low-temperature conditions. The structure-controlled CG anode prepared via a one-step aerosol drying process shows a remarkable rate-capability by delivering ≈206 mAh g^–1 at a high current density of 10 A g^–1 at room temperature. At an extremely low temperature of −40 °C, CG anode still exhibits a high capacity of ≈154 mAh g^–1 at 0.01 A g^–1 with excellent rate-capability and cycling stability. A combination of electrochemical studies and density functional theory (DFT) reveals that the superior performance of CG anode stems from the dominant surface-controlled charge storage mechanism at various defect sites. This study establishes the effective utilization of the surface-controlled charge storage mechanism through structure-controlled graphene as a promising strategy to improve the charge storage kinetics and stability under low-temperature conditions.     

Empirical millimeter-wave wideband propagation characteristics of high-speed train environments

Owing to the difficulties associated with conducting millimeter-wave (mmWave) field measurements, especially in high-speed train (HST) environments, most propagation channels for mmWave HST have been studied using methods based on simulation rather than measurement. In this study, considering a linear cell layout in which base stations are installed along a railway, measurements were performed at 28 GHz with a speed up to 170 km/h in two prevalent HST scenarios: viaduct and tunnel scenarios. By observing the channel impulse responses, we could identify single- and double-bounced multipath components (MPCs) caused by railway static structures such as overhead line equipment. These MPCs affect the delay spread and Doppler characteristics significantly. Moreover, we observed distinct path loss behaviors for the two scenarios, although both are considered line-of-sight (LoS) scenarios. In the tunnel scenario, the path loss exponent (PLE) is 1.3 owing to the waveguide effect, which indicates that the path loss is almost constant with respect to distance. However, the LoS PLE in the viaduct scenario is 2.46, which is slightly higher than the free-space loss.     

Temporal fairness guarantee in multi-rate wireless LANs for per-flow protection

Wireless LAN technologies such as IEEE 802.11a and 802.11b support high bandwidth and multi-rate data transmission to match the channel condition (i.e., signal to noise ratio). While some wireless packet fair queuing algorithms to achieve the per-flow throughput fairness have been proposed, they are not appropriate for guaranteeing QoS in multi-rate wireless LAN environments. We propose a wireless packet scheduling algorithm that uses the multi-state (multi-rate) wireless channel model and performs packet scheduling by taking into account the channel usage time of each flow. The proposed algorithm aims at per-flow protection by providing equal channel usage time for each flow. To achieve the per-flow protection, we propose a temporally fair scheduling algorithm called Contention-Aware Temporally fair Scheduling (CATS) which provides equal channel usage time for each flow. Channel usage time is defined as the sum of the packet transmission time and the contention overhead time due to the CSMA/CA mechanism. The CATS algorithm provides per-flow protection in wireless LAN environments where the channel qualities of mobile stations are dynamic over time, and where the packet sizes are application-dependent. We also extend CATS to Decentralized-CATS (D-CATS) to provide per-flow protection in the uplink transmission. Using an NS-2 simulation, we evaluate the fairness property of both CATS and D-CATS in various scenarios. Simulation results show that the throughput of mobile stations with stable link conditions is not degraded by the mobility (or link instability) of other stations or by packet size variations. D-CATS also shows less delay and less delay jitter than FIFO. In addition, since D-CATS can coordinate the number of contending mobile stations, the overall throughput is not degraded as the number of mobile stations increases. This work was supported in part by the Brain Korea 21 project of Ministry of Education and in part by the National Research Laboratory project of Ministry of Science and Technology, 2004, Korea.     

A 2.4-GHz Low-Power Low-IF Receiver and Direct-Conversion Transmitter in 0.18-μm CMOS for IEEE 802.15.4 WPAN Applications

In this paper, a low-power low-IF receiver and a direct-conversion transmitter (DCT) suitable for the IEEE standard 802.15.4 radio system at the 2.4-GHz band are presented in 0.18-mum deep n-well CMOS technology. By using vertical NPN (V-NPN) bipolar junction transistors in the baseband analog circuits of the low-IF receiver, the image rejection performance is improved and the power consumption is reduced. In addition, by applying the V-NPN current mirrored technique in a DCT, the carrier leakage is reduced and the linearity performance is improved. The receiver has 10 dB of noise figure, -15 dBm of third-order input intercept point, and 35 dBc of image rejection. The transmitter has more than -2 dBm of transmit output power, -35 dBc of local oscillator leakage, and -46 dBc of the transmit third harmonic component. The receiver and transmitter dissipate 6 and 9 mA from a 1.8-V supply, respectively