Characteristics of solderable electrically conductive adhesives (ECAs) for electronic packaging

This study investigated the effect of the viscosity of the ECAs using a low-melting-point alloy (LMPA) filler on its bonding characteristics. The curing behaviors of the ECAs were determined using Differential Scanning Calorimetry (DSC), and ECA temperature-dependant viscosity characteristics were observed using a torsional parallel rheometer. The wetting test was conducted to investigate the reduction capability of ECAs and the flow-coalescence-wetting behavior of the LMPAs in ECAs. Electrical and mechanical properties were determined and compared to those with commercial ECAs and eutectic tin/lead (Sn/Pb) solder. In the metallurgically interconnected Quad Flat Package (QFP) joint, a typical scallop-type Cu–Sn intermetallic compound (IMC) layer formed at the upper SnBi/Cu interface after curing process. On the other hand, a (Cu, Ni)₆Sn₅ IMC layer formed on the SnBi/ENIG interface. In addition, the fracture surface exhibited by cleavage fracture mode and the fracture was propagated along the Cu–Sn IMC/SnBi interface. The extremely low-level viscosity of ECAs had a significant influence on the flow-coalescence-wetting behavior of the LMPAs in ECAs and also on the interconnection properties. Stable interconnected assemblies showed good electrical and mechanical properties.     

Three-phase unbalanced-voltage compensators

In this paper, three-phase unbalanced-voltage compensators using ac choppers are proposed. The proposed three-phase unbalanced-voltage compensators are made up of three single-phase ac choppers and transformers for unbalanced-voltage compensation and output voltage regulation. The proposed compensators use ac choppers which solve the commutation problem, limit the switch voltage stress to the maximum line voltage, and also raise efficiency using regenerative dc snubbers. Compared with previous unbalanced-voltage compensators that use complex voltage source inverters, the proposed unbalanced-voltage compensators use ac choppers and utilize source or output line voltages in 30° phase shift with the phase voltages as the input of the ac chopper. Then, the proposed compensators give high efficiency, fast dynamics, simple power circuit, and reduced control circuit. It is also shown via some simulation and experimental results that the presented unbalanced-voltage compensators give good dynamic and steady state performances.     

A digit-serial multiplier for finite field GF(2/sup m/)

In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF(2/sup m/) using the standard basis representation. From the least significant bit first multiplication algorithm, we obtain a new dependence graph and design an efficient digit-serial systolic multiplier. If input data come in continuously, the proposed array can produce multiplication results at a rate of one every /spl lceil/m/L/spl rceil/ clock cycles, where L is the selected digit size. Analysis shows that the computational delay time of the proposed architecture is significantly less than the previously proposed digit-serial systolic multiplier. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation.     

L-shape 2-dimensional arrival angle estimation with propagator method

It is known that computational loads of the propagator method (PM) can be significantly smaller, e.g., one or two order, than those of MUSIC and ESPRIT because the PM does not require any eigenvalue decomposition (EVD) of the cross-correlation matrix and singular value decomposition (SVD) of the received data. However, the PM of the parallel shape array has nonnegligible drawbacks such as 1) requirement of pair matching between the 2-D azimuth and elevation angle estimation which is an exhaustive search and 2) estimation failure problems when elevation angles are between 70/spl deg/ and 90/spl deg/. The purpose of this paper is to show a way to remove these problems in the PM without additional computational loads. This paper will employ one or two L-shape arrays because the parallel shape used in the PM may cause the aforesaid problems. Simulation results verify that the PM with one or two L-shape configurations can remove these problems and improve the performance of the PM significantly, e.g., almost 5 dB in signal to noise ratio for the parameters used in this paper.     

The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application

The impact of CMOS technology scaling on the various radio frequency (RF) circuit components such as active, passive and digital circuits is presented. Firstly, the impact of technology scaling on the noise and linearity of the low-noise amplifier (LNA) is thoroughly analyzed. Then two new circuits, i.e., CMOS complementary parallel push-pull (CCPP) circuit and vertical-NPN (V-NPN) circuit for direct-conversion receiver (DCR), are introduced. In CCPP, the high RF performance of pMOS comparable to nMOS provides single ended differential RF signal processing capability without the use of a bulky balun. The use of parasitic V-NPN bipolar transistor, available in triple well CMOS technology, has shown to provide more than an order of magnitude improvement in 1/f noise and dc offset related problems, which have been the bottleneck for CMOS single chip integration. Then CMOS technology scaling for various passive device performances such as the inductor, varactor, MIM capacitor, and switched capacitor, is discussed. Both the forward scaling of the active devices and the inverse scaling of interconnection layer, i.e., more interconnection layers with effectively thicker total dielectric and metal layers, provide very favorable scenario for all passive devices. Finally, the impact of CMOS scaling on the various digital circuits is introduced, taking the digital modem blocks, the various digital calibration circuits, the switching RF power amplifier, and eventually the software defined radio, as examples.     

Compact slotted planar inverted-F RFID tag mountable on metallic objects

A compact slotted PIFA-type RFID tag (900 MHz) mountable on metallic objects is presented. The proposed structure can be easily matched to most microchips and facilitates their attachment on its slot. The performance of the tag is evaluated by monitoring its radar cross-sections (RCSs) for various incident angles and chip impedances. The measured detection distance is 4 m.     

A Highly Efficient GaAs HBT MMIC Balanced Power Amplifier for W‐CDMA Handset Applications

A highly efficient and compactly integrated balanced power amplifier (PA) for W‐CDMA handset applications is presented. To overcome the size limit of a typical balanced PA, a bulky input divider is integrated into a PA MMIC, and a complex output network is replaced with simple lumped‐element networks. For efficiency improvement at the low output power level, one of the two amplifiers in parallel is deactivated and the other is partially operated with corresponding load impedance optimization. The implemented PA shows excellent average current consumption of 34.5 mA in urban and 56.3 mA in suburban environments, while exhibiting very good load‐insensitivity under condition of VSWR=4:1.     

Evaluation of 1/f Noise Characteristics for Si‐Based Infrared Detection Materials

Silicon antimony films are studied as resistors for uncooled microbolometers. We present the fabrication of silicon films and their alloy films using sputtering and plasma‐enhanced chemical vapor deposition. The sputtered silicon antimony films show a low 1/f noise level compared to plasma‐enhanced chemical vapor deposition (PECVD)‐deposited amorphous silicon due to their very fine nanostructure. Material parameter K is controlled using the sputtering conditions to obtain a low 1/f noise. The calculation for specific detectivity assuming similar properties of silicon antimony and PECVD amorphous silicon shows that silicon antimony film demonstrates an outstanding value compared with PECVD Si film.     

Small molecule interlayer for solution processed phosphorescent organic light emitting device

Using a 4,4′,4′′-tris(N-carbazolyl)-triphenylamine (TCTA) small molecule interlayer, we have fabricated efficient green phosphorescent organic light emitting devices by solution process. Significantly a low driving voltage of 3.0 V to reach a luminance of 1000 cd/m² is reported in this device. The maximum current and power efficiency values of 27.2 cd/A and 17.8 lm/W with TCTA interlayer (thickness 30 nm) and 33.7 cd/A and 19.6 lm/W with 40 nm thick interlayer are demonstrated, respectively. Results reveal a way to fabricate the phosphorescent organic light emitting device using TCTA small molecule interlayer by solution process, promising for efficient and simple manufacturing.     

Cyclic delay diversity with frequency domain turbo equalization for uplink fast fading channels

Cyclic delay diversity (CDD) is an attractive diversity technique due to its low complexity and compatibility to existing wireless communication systems. This letter proposes a CDD with frequency domain turbo equalization (FDTE) for single carrier (SC) transmission, in order to achieve the full spatial diversity of frequency-selective multi-antenna channels. The frequency diversity inherent in SC is picked up from the increased channel selectivity of CDD. The noise or intersymbol interference enhanced by equalization for highly selective channels is then mitigated through applying FDTE at the receiver. Simulation results show that the performance of proposed system approaches the corresponding orthogonal spacetime block coding (STBC) system in slowly fading channels without any data rate loss, and considerably outperforms the STBC system in fast fading channels.