A 30-b integrated logarithmic number system processor

The authors describe an integrated processor that performs addition and subtraction of 30-b numbers in the logarithmic number system (LNS). This processor offers 5-MOPS performance in 3-μm CMOS technology, and is implemented in a two-chip set comprising 170 K transistors. Two techniques are used to achieve this precision in a moderate circuit area. Linear approximation of the LNS arithmetic functions using logarithmic arithmetic is shown to be simple due to the particular functions involved. A segmented approach to linear approximation minimizes the amount of table space required. Subsequent nonlinear compression of each lookup table leads to a further reduction in table size. The result is that a factor of 285 reduction in table size is achieved, compared to previous techniques. The circuit area of the implementation is minimized by optimizing the table parameters, using a computer program that accurately models ROM area. The implementation is highly pipelined, and produces one result per clock cycle using a ten-stage pipeline     

Single chip for imaging, colour segmentation, histogramming andtemplate matching

A 128(H)×64(V)×RGB CMOS imager is integrated with region-of-interest selection, RGB-to-HSI transformation, HSI-based pixel segmentation, 36 bin×12 bit HSI histogramming and sum-of-absolute-difference template matching. 32 learned colour templates are stored and compared to each image. Running at 30 fps, it uses 1 mW     

Direct‐Write Assembly of Microperiodic Silk Fibroin Scaffolds for Tissue Engineering Applications

Three–dimensional, microperiodic scaffolds of regenerated silk fibroin have been fabricated for tissue engineering by direct ink writing. The ink, which consisted of silk fibroin solution from the Bombyx mori silkworm, was deposited in a layer‐by‐layer fashion through a fine nozzle to produce a 3D array of silk fibers of diameter 5 µm. The extruded fibers crystallized when deposited into a methanol‐rich reservoir, retaining a pore structure necessary for media transport. The rheological properties of the silk fibroin solutions were investigated and the crystallized silk fibers were characterized for structure and mechanical properties by infrared spectroscopy and nanoindentation, respectively. The scaffolds supported human bone marrow‐derived mesenchymal stem cell (hMSC) adhesion, and growth. Cells cultured under chondrogenic conditions on these scaffolds supported enhanced chondrogenic differentiation based on increased glucosaminoglycan production compared to standard pellet culture. Our results suggest that 3D silk fibroin scaffolds may find potential application as tissue engineering constructs due to the precise control of their scaffold architecture and their biocompatibility.     

Printing Reconfigurable Bundles of Dielectric Elastomer Fibers

Active soft materials that change shape on demand are of interest for a myriad of applications, including soft robotics, biomedical devices, and adaptive systems. Despite recent advances, the ability to rapidly design and fabricate active matter in complex, reconfigurable layouts remains challenging. Here, the 3D printing of core-sheath-shell dielectric elastomer fibers (DEF) and fiber bundles with programmable actuation is reported. Complex shape morphing responses are achieved by printing individually addressable fibers within 3D architectures, including vertical coils and fiber bundles. These DEF devices exhibit resonance frequencies up to 700 Hz and lifetimes exceeding 2.6 million cycles. The multimaterial, multicore-shell 3D printing method opens new avenues for creating active soft matter with fast programable actuation.     

Magnetic field spatial Fourier analysis: A new opportunity for high resolution current localization

Magnetic microscopy has proven its usefulness throughout the years. It allows current localization with a certain degree of precision by using an inversion algorithm to invert the Biot–Savart law. The goal is to obtain the current distribution once the magnetic field is given. However, in order to obtain a stable solution, the magnetic data is severely low-pass filtered in the spatial Fourier domain, and some important information is lost. In this paper, the contribution given by the different spatial frequencies was studied: it was demonstrated how this information can be used to obtain additional information regarding the position of the currents. A comparative study between the theoretical approach and the application to the measurements is also shown.     

Performance and Modeling of the MWIR HgCdTe Electron Avalanche Photodiode

The operation of the mid-wave infrared (MWIR) HgCdTe cylindrical electron injection avalanche photodiode (e-APD) is described. The measured gain and excess noise factor are related to the collection region fill factor. A two-dimensional diffusion model calculates the time-dependent response and steady-state pixel point spread function for cylindrical diodes, and predicts bandwidths near 1 GHz for small geometries. A 2 μm diameter spot scan system was developed for point spread function and crosstalk measurements at 80 K. An electron diffusion length of 13.4 μm was extracted from spot scan data. Bandwidth data are shown that indicate bandwidths in excess of 300 MHz for small unit cells geometries. Dark current data, at high gain levels, indicate an effective gain normalized dark density count as low as 1000 counts/μs/cm² at an APD gain of 444. A junction doping profile was determined from capacitance–voltage data. Spectral response data shows a gain-independent characteristic.     

Noise performance comparison for third and fourth order cascaded sigma-delta modulators having parameter tolerance errors

A parameter tolerance, signal to noise ratio comparison is made between the MASH third order sigma-delta modulator structure and a new fourth order cascaded structure. The fourth order structure meets the required performance specification with wider parameter tolerances, allowing easier integration using hybrid CMOS technology.<>     

Implementing policy in enterprise networks

There is a need for a general policy management architecture that can guide one in understanding and implementing policy in diverse management applications. The question of policy in network management has evolved since the early '70s concern with monitoring and controlling the access rights of multiple users and resources in large distributed systems. It is now generally acknowledged that policy also plays an important role in other areas of network management, including configuration, accounting, fault, and performance management. Furthermore, it is agreed that a general policy framework is needed for controlling the behavior of the agents the enterprise network comprises, including network users, administrators, troubleshooters, the applications running on the network, and the operational parameters of network hardware. The authors present a framework for understanding and implementing policy in the management of enterprise networks. We describe typical network scenarios in which policy plays a role, a general architecture for policy management and the components and operations of the architecture at a level of abstraction that renders it applicable to specific management tasks which require policy. We also provide an example of the architecture in configuration management. The article draws from work on policy management, including two ESPRIT projects     

Multiservice platforms for data services

The potential for broadband and data services is large and continues to expand for the foreseeable future. Consideration of the cost-effective delivery and support of both new, advanced services, as well as existing services, has led to the driver for multiservice platforms (MSPs). The cost effectiveness results from the MSP potential to share network bandwidth between services, offer a potential simplification of the operational support systems (OSS), and enable new service features and functions. A generic ATM-based MSP is described in this paper where issues of service support, service interworking, operations and maintenance, and network architecture are discussed. The paper is intended as a tutorial on the concepts.     

A digital background calibration technique for time-interleavedanalog-to-digital converters

A 10-bit 40-Msample/s two-channel parallel pipelined ADC with monolithic digital background calibration has been designed and fabricated in a 1 μm CMOS technology. Adaptive signal processing and extra resolution in each channel are used to carry out digital background calibration. Test results show that the ADC achieves a signal-to-noise-and-distortion ratio of 55 dB for a 0.8-MHz sinusoidal input, a peak integral nonlinearity of 0.34 LSB, and a peak differential nonlinearity of 0.14 LSB, both at a 10-bit level. The active area is 42 mm², and the power dissipation is 565 mW from a 5 V supply