Adaptive control of surviving symbol replica candidates in QRM-MLD for OFDM MIMO multiplexing

This paper proposes adaptive control of the number of surviving symbol replica candidates, S/sub m/ (m denotes the stage index), based on the minimum accumulated branch metric of each stage in maximum-likelihood detection employing QR decomposition and the M-algorithm (QRM-MLD) in orthogonal frequency-division multiplexing with multiple-input-multiple-output (MIMO) multiplexing. In the proposed algorithm, S/sub m/ at the mth stage (1/spl les/m/spl les/N/sub t/, N/sub t/ is the number of transmission antenna branches) is independently controlled using the threshold value calculated from the minimum accumulated branch metric at that stage and the estimated noise power. We compared the computational complexity of QRM-MLD employing the proposed algorithm with that of conventional methods at the same average packet error rate assuming the information bit rate of 1.048 Gb/s in a 100-MHz channel bandwidth (i.e., frequency efficiency of approximately 10 bit/s/Hz) using 16QAM modulation and turbo coding with the coding rate of 8/9 in 4-by-4 MIMO multiplexing. Computer simulation results show that the average computational complexity of the branch metrics, i.e., squared Euclidian distances, of the proposed adaptive independent S/sub m/ control method is decreased to approximately 38% that of the conventional adaptive common S/sub m/ control and to approximately 30% that of the fixed S/sub m/ method (S/sub m/=M=16), assuming fair conditions such that the maximum number of surviving symbol replicas at each stage is set to M/spl circ/=16.     

Second-Order Approximation for DOA Estimation of Near-Field Sources

The direction-of-arrival estimation of near-field sources can be formulated as a multidimensional nonlinear optimization problem, where a performance index is minimized with respect to azimuth, range, and source power. For the single source case, under the assumption that the range is relatively larger than the interelement distance, we use the second-order approximation to derive a simpler performance index parameterized by azimuth only. The minimization of the new index is easier than that of the original one parameterized by azimuth, range, and source power. Moreover, the proposed method considers the degradation of signal powers, giving more accurate estimation results. Also for the multiple source case, an efficient computation method is developed by using the second-order approximation.     

Defective bone remodelling in osteoprotegerin-deficient mice

Previous studies have reported enhanced osteoclastogenesis, increased bone resorption and osteoporosis in osteoprotegerin (OPG)-deficient mice. In the present study, we show that the tibial epiphyses contain abundant, thin trabeculae lined with numerous osteoclasts and cuboidal osteoblasts. The increase in osteoblasts and osteoclasts was associated with a dramatic increase in calcein labelling of the mineralization fronts and replacement of much of the intertrabecular marrow with numerous alkaline phosphatase-positive preosteoblasts. Furthermore, the discrete, linear cement lines seen in wild-type mice were replaced by a randomly oriented meshwork of cement lines that were stained intensely for tartrate-resistant acid phosphatase and osteopontin in the OPG-/- mice. These indices of accelerated bone remodelling in mutant bone were associated with irregular trabecular surfaces, a disorganized collagen matrix interspersed with amorphous ground substance and numerous fissures between old and new bone. In total, these observations indicate that enhanced osteoclastic activity in OPG-/- epiphyses led to a coupled increase in osteoblast differentiation and activity and an increase in bone remodelling. The high bone turnover, disorganized matrix and impaired attachment of new to old bone in the cement lines in OPG-/- mice appear to cause bone fragility.     

High-performance embedded SOI DRAM architecture for the low-powersupply

This paper presents the high-performance DRAM array and logic architecture for a sub-1.2-V embedded silicon-on-insulator (SOI) DRAM. The degradation of the transistor performance caused by boosted wordline voltage level is distinctly apparent in the low voltage range. In our proposed stressless SOI DRAM array, the applied electric field to the gate oxide of the memory-cell transistor can he relaxed. The crucial problem that the gate oxide of the embedded-DRAM process must be thicker than that of the logic process can be solved. As a result, the performance degradation of the logic transistor can be avoided without forming the gate oxides of the memory-cell array and the logic circuits individually. In addition, the data retention characteristics can be improved. Secondly, we propose the body-bias-controlled SOI-circuit architecture which enhances the performance of the logic circuit at sub-1.2-V power supply voltage, Experimental results verify that the proposed circuit architecture has the potential to reduce the gate-delay time up to 30% compared to the conventional one. This proposed architecture could provide high performance in the low-voltage embedded SOI DRAM     

Development of quasi-end-fired waveguide plastic dye laser

A quasi-end-fire (QEF) pumping scheme was proposed and studied as a novel laser-pumping-scheme for a laser-dye-doped plastic waveguide laser with distributed feedback. This pumping scheme resembled longitudinal pumping, but also has the advantage of controllable absorption length of the injected pump beam. A first demonstration of the QEF was performed and the pumping beam controlling was also investigated.     

WDM upgrading of an installed submarine optical amplifier system

This paper describes the WDM upgrading of a submarine optical amplifier system installed for single-channel transmission in commercial use. The key technologies used include 10-Gb/s high-speed forward error correction, preemphasis to overcome the optical passband-width constraint, optimized signal pulse format that leads to partial return-to-zero (PRZ) signaling, and dispersion compensation to suppress the degradation caused by fiber nonlinearity and dispersion. It also reports field experimental results on upgraded system performance. The results confirm that simply upgrading the terminal equipment allows the transmission capacity of a submersed line consisting of submarine repeaters and cables to be flexibly increased from 10 Gb/s to 40 Gb/s per fiber pair     

An 8-b slice GaAs bus logic LSI for a high-speed parallelprocessing system

An 8-b slice GaAs bus logic LSI (BL) has been developed for a high-speed interconnection network in a multiple-instruction multiple-data stream (MIMD) parallel processing system. The BL has been designed using a novel standard-cell approach called the building-cell methodology, which leads to a high integrated density of 25000 devices in a 7×7-mm² chip. The BL consists of 3376 logic gates and a 76-b dual-port register file (RF), which has as a new function a multi-address read/write operation for efficient data transfer. The BL was fabricated by a 0.8-μm WN_x gate LDD (lightly doped drain) MESFET process, and fully functionally tested with an average yield of 20%. A 10-ns cycle time operation was achieved with a power dissipation of 5.5 W. This result reveals that a network with 256 GaAs BLs and 64 processor units can realize a maximum data transfer rate of 2.56 Gbyte/s     

Photodetectors monolithically integrated on SOI substrate foroptical pickup using blue or near-infrared semiconductor laser

We made photodetectors on a silicon-on-insulator (SOI) substrate by a 0.35-μm BiCMOS fabrication process to detect the signal light used in an optical disk system. Investigating their characteristics at two wavelengths, 410 and 780 nm, for different structures, we found that the thickness of the silicon crystalline layer on the insulator strongly affected the frequency response at the longer wavelength, while the cutoff frequency was over 500 MHz for the shorter wavelength. We also simulated the frequency response     

Compaction of IDDQ Test Sequence Using Reassignment Method

IDDQ testing is an effective method for detecting short faults of CMOS circuits. Since IDDQ testing requires the measurement of current, the testing time of IDDQ testing is longer than that of logical testing. In this paper, we proposed an IDDQ test compaction method for internal short faults of gates in sequential circuits by using the reassignment method of signal values. Experimental results show that test sequences generated by weighted random vectors can be reduced to short sequences with less computation time.