云环境下的IT服务管理研究

云计算技术的出现让企业面临着新的选择和决策.在优势和风险并存的情况下,企业如何从云环境中获取和管控所需要的IT服务是亟需研究的问题.文中基于云服务的特点,对企业的云服务管理要素进行了分析,参考ITIL（Information Technology Infrastructure Library,信息技术基础架构库）理论,提出了云环境下对服务匹配和服务实施过程的管控方法.最后构建了面向企业的云服务管理模型,以供企业进行云环境下的IT建设时参考.     

Co‐Interlayer Engineering toward Efficient Green Quasi‐Two‐Dimensional Perovskite Light‐Emitting Diodes

With respect to three‐dimensional (3D) perovskites, quasi‐two‐dimensional (quasi‐2D) perovskites have unique advantages in light‐emitting devices (LEDs), such as strong exciton binding energy and good phase stability. Interlayer ligand engineering is a key issue to endow them with these properties. Rational design principles for interlayer materials and their processing techniques remain open to investigation. A co‐interlayer engineering strategy is developed to give efficient quasi‐2D perovskites by employing phenylbutylammonium bromide (PBABr) and propylammonium bromide (PABr) as the ligand materials. Preparation of these co‐interlayer quasi‐2D perovskite films is simple and highly controllable without using antisolvent treatment. Crystallization and morphology are readily manipulated by tuning the ratio of co‐interlayer components. Various optical techniques, including steady and ultrafast transient absorption and photoluminescence spectroscopies, are used to investigate their excitonic properties. Photoluminescence quantum yield (PLQY) of the perovskite film is dramatically improved to 89% due to the combined optimization of exciton binding energy and suppression of trap state formation. Accordingly, a high current efficiency of 66.1 cd A^?1 and an external quantum efficiency of 15.1% are achieved for green co‐interlayer quasi‐2D perovskite LEDs without using any light out‐coupling techniques, indicating that co‐interlayer engineering is a simple and effective approach to develop high‐performance perovskite electroluminescence devices.     

Connection Admission Control in the UTRAN Transport Network

In this paper we propose a Connection Admission Control (CAC) algorithm to provide Quality of Service (QoS) in UMTS Terrestrial Radio Access Networks (UTRAN). In UTRAN, the main QoS requirement is to ensure low packet delays. The CAC algorithm works with priority scheduling, which is used for QoS differentiation. We give a detailed investigation on the performance implications of applying priority scheduler. We provide novel closed-form formulae which are fast, simple and accurate enough for practical implementation of the CAC. A comprehensive performance evaluation study with illustrative numerical examples is also presented. The results are validated by simulations.     

辅助天线不同排列形式及位置变化对SLC影响

本文研究了当辅助天线不同摆放形式及位置变化对旁瓣相消性能的影响,给出存在幅相误差及位置误差时数学模型,讨论存在误差时旁瓣相消性能变化,并在二维自适应旁瓣对消中使用降维方法求解权,最后计算机仿真分析证明了相关结论的正确性.     

Methodological principles of T wave alternans analysis: a unified framework

Visible T wave alternans (TWA) in the electrocardiogram (ECG) had been regarded as an infrequent phenomenon during the first 80 years of electrocardiography. Nevertheless, computerized analysis changed this perception. In the last two decades, a variety of techniques for automatic TWA analysis have been proposed. These techniques have allowed researchers to detect nonvisible TWA in a wide variety of clinical and experimental conditions. Such studies have recently shown that TWA is related to cardiac instability and increased arrhythmogenicity. Comparison of TWA analysis methods is a difficult task due to the diversity of approaches. In this paper, we propose a unified framework which holds the existing methods. In the light of this framework, the methodological principles of the published TWA analysis schemes are compared and discussed. This framework may have an important role to develop new approaches to this problem.     

一种主从式多处理器间数据传输方案

介绍了一种主从式多处理器间数据传输的方案，对处理器间通信的协议和设备驱动程序进行了详细的描述。     

Nitride-Based Schottky Barrier Sensor Module With High Electrostatic Discharge Reliability

In this study, we proposed and realized a nitride-based Schottky barrier sensor module with high electrostatic discharge (ESD) reliability. By including a Si-based ESD protection chip into the module, we can significantly enhance endurable ESD voltages under both forward and reverse human-body-mode (HBM) ESD stresses. It was found that the fabricated module can endure reverse HBM ESD stress of 7.5 KV and forward HBM ESD stress larger than 8 KV. It was also found that the inclusion of the Si-based ESD protection chip will not result in a decrease in detector responsivity     

A Time-Domain Digital-Intensive Built-In Tester for Analog Circuits

To solve test challenges in nanometer CMOS technologies, a time-domain digital-intensive built-in tester for analog circuits is proposed. The compact tester allows characterizations of AC response and DC gain for various analog circuits which have a low-pass frequency characteristic. By applying ramp signals to stimulate the circuit under test and measuring slopes and time delays of its responses, the testing can be simple and robust over process-voltage-temperature variations. Also, it is well suited for nanometer technologies because of its digital-intensive implementation. The tester was fabricated in 65 nm standard CMOS process and occupies 0.026 mm².