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91.
Giuliano De Rossi 《Computational Economics》2010,36(1):1-16
This paper shows how to build in a computationally efficient way a maximum simulated likelihood procedure to estimate the
Cox–Ingersoll–Ross model from multivariate time series. The advantage of this estimator is that it takes into account the
exact likelihood function while avoiding the huge computational burden associated with MCMC methods and without the ad hoc
assumption that certain bond yields are measured without error. The proposed methodology is implemented and tested on simulated
data. For realistic parameter values the estimator seems to have good small sample properties, compared to the popular quasi
maximum likelihood approach, even using moderate simulation sizes. The effect of simulation errors does not seem to undermine
the estimation procedure. 相似文献
92.
93.
Claudio Brunelli Fabio Garzia Davide Rossi Jari Nurmi 《Journal of Systems Architecture》2010,56(1):38-47
Signal processors exploiting ASIC acceleration suffer from sky-rocketing manufacturing costs and long design cycles. FPGA-based systems provide a programmable alternative for exploiting computation parallelism, but the flexibility they provide is not as high as in processor-oriented architectures: HDL or C-to-HDL flows still require specific expertise and a hardware knowledge background. On the other hand, the large size of the configuration bitstream and the inherent complexity of FPGA devices make their dynamic reconfiguration not a very viable approach. Coarse-grained reconfigurable architectures (CGRAs) are an appealing solution but they pose implementation problems and tend to be application specific. This paper presents a scalable CGRA which eases the implementation of algorithms on field programmable gate array (FPGA) platforms. This design option is based on two levels of programmability: it takes advantage of performance and reliability provided by state-of-the-art FPGA technology, and at the same time it provides the user with flexibility, performance and ease of reconfiguration typical of standard CGRAs. The basic cell template provides advanced features such as sub-word SIMD integer and floating-point computation capabilities, as well as saturating arithmetic. Multiple reconfiguration contexts and partial run-time reconfiguration capabilities are provided, tackling this way the problem of high reconfiguration overhead typical of FPGAs. Selected instances of the proposed architecture have been implemented on an Altera Stratix II EP2S180 FPGA. On this system, we mapped some common DSP, image processing, 3D graphics and audio compression algorithms in order to validate our approach and to demonstrate its effectiveness by benchmarking the benefits achieved. 相似文献
94.
Ciullo D. Garcia M.A. Horvath A. Leonardi E. Mellia M. Rossi D. Telek M. Veglia P. 《Multimedia, IEEE Transactions on》2010,12(1):54-63
Early P2P-TV systems have already attracted millions of users, and many new commercial solutions are entering this market. Little information is however available about how these systems work, due to their closed and proprietary design. In this paper, we present large scale experiments to compare three of the most successful P2P-TV systems, namely PPLive, SopCast and TVAnts. Our goal is to assess what level of "network awareness" has been embedded in the applications. We first define a general framework to quantify which network layer parameters leverage application choices, i.e., what parameters mainly drive the peer selection and data exchange. We then apply the methodology to a large dataset, collected during a number of experiments where we deployed about 40 peers in several European countries. From analysis of the dataset, we observe that TVAnts and PPLive exhibit a mild preference to exchange data among peers in the same autonomous system the peer belongs to, while this clustering effect is less intense in SopCast. However, no preference versus country, subnet or hop count is shown. Therefore, we believe that next-generation P2P live streaming applications definitively need to improve the level of network-awareness, so to better localize the traffic in the network and thus increase their network-friendliness as well. 相似文献
95.
Navigational features have been largely recognized as fundamental for graph database query languages. This fact has motivated several authors to propose RDF query languages with navigational capabilities. In this paper, we propose the query language nSPARQL that uses nested regular expressions to navigate RDF data. We study some of the fundamental properties of nSPARQL and nested regular expressions concerning expressiveness and complexity of evaluation. Regarding expressiveness, we show that nSPARQL is expressive enough to answer queries considering the semantics of the RDFS vocabulary by directly traversing the input graph. We also show that nesting is necessary in nSPARQL to obtain this last result, and we study the expressiveness of the combination of nested regular expressions and SPARQL operators. Regarding complexity of evaluation, we prove that given an RDF graph G and a nested regular expression E, this problem can be solved in time O(|G||E|). 相似文献
96.
Po-Ying Yeh Nicholas A. A. Rossi Jayachandran N. Kizhakkedathu Mu Chiao 《Microfluidics and nanofluidics》2010,9(2-3):199-209
A poly(dimethylsiloxane) (PDMS)-based functional microfluidic device containing a charged matrix of PDMS pillar arrays grafted with hyperbranched polyglycerols (HPGs) was developed. Samples of PDMS were modified with allylamine plasma to form amine groups on the surface prior to the covalent grafting of succinimdyl ester-functionalized HPGs. The anionic functionality of the PDMS channel matrices was developed by altering the number of carboxyl groups present on the HPGs. The grafting of HPGs onto PDMS plates was investigated via contact angle measurement and attenuated total reflectance-Fourier transform infrared spectroscopy (ATR-FTIR), while the grafting of the inside channel was investigated by electroosmotic flow (EOF) measurements. The charge density on grafted HPG was optimized to minimize the nonspecific protein adsorption and increase the selective capture of positively charged proteins. A proof-of-concept device was fabricated on PDMS and demonstrated that the device selectively captures positively charged protein (avidin) from a mixture of bovine serum albumin (BSA)-avidin at pH 7.4 in phosphate buffered saline (PBS). In order to increase the capture efficiency of the proteins in this PDMS-based device, pillar arrays have been fabricated within the channel. As a demonstration, the new device separated two proteins with an avidin capture efficiency of 100 ± 2.95% per 3 min from a 0.02 mg/ml protein solution (avidin:BSA wt ratio: 1:1). This new microfluidic-based device shows a great deal of promise as a tool for protein capture and analysis. 相似文献
97.
Mitsuo Takaki Diego Cavalcanti Rohit Gheyi Juliano Iyoda Marcelo d’Amorim Ricardo B. C. Prudêncio 《Innovations in Systems and Software Engineering》2010,6(3):243-253
The complexity of constraints is a major obstacle for constraint-based software verification. Automatic constraint solvers are fundamentally incomplete: input constraints often build on some undecidable theory or some theory the solver does not support. This paper proposes and evaluates several randomized solvers to address this issue. We compared the effectiveness of a symbolic solver (CVC3), a random solver, two heuristic search solvers, and seven hybrid solvers (i.e. mix of random, symbolic, and heuristic solvers). We evaluated the solvers on a benchmark generated with a concolic execution of 9 subjects. The performance of each solver was measured by its precision, which is the fraction of constraints that the solver can find solution out of the total number of constraints that some solver can find solution. As expected, symbolic solving subsumes the other approaches for the 4 subjects that only generate decidable constraints. For the remaining 5 subjects, which contain undecidable constraints, the hybrid solvers achieved the highest precision (fraction of constraints that a solver can find a solution out of the total number of satisfiable constraints). We also observed that the solvers were complementary, which suggests that one should alternate their use in iterations of a concolic execution driver. 相似文献
98.
Arnaud Grasset Philippe Millet Philippe Bonnot Sami Yehia Wolfram Putzke-Roeming Fabio Campi Alberto Rosti Michael Huebner Nikolaos S. Voros Davide Rossi Henning Sahlbach Rolf Ernst 《International journal of parallel programming》2011,39(3):328-356
Reconfigurable computing offers a wide range of low cost and efficient solutions for embedded systems. The proper choice of the reconfigurable device, the granularity of its processing elements and its memory architecture highly depend on the type of application and their data flow. Existing solutions either offer fine grain FPGAs, which rely on a hardware synthesis flow and offer the maximum degree of flexibility, or coarser grain solutions, which are usually more suitable for a particular type of data flow and applications. In this paper, we present the MORPHEUS architecture, a versatile reconfigurable heterogeneous System-on-Chip targeting streaming applications. The presented architecture exploits different reconfigurable technologies at several computation granularities that efficiently address the different applications needs. In order to efficiently exploit the presented architecture, we implemented a complete software solution to map C applications to the reconfigurable architecture. In this paper, we describe the complete toolset and provide concrete use cases of the architecture. 相似文献
99.
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a
bottleneck that prevents these architectures from scaling to a larger number of cores. Tiled CMPs offer better scalability
by integrating relatively simple cores with a lightweight point-to-point interconnect. However, such interconnects make snooping
impractical and, thus, require alternative solutions to cache coherence. In this article, we investigate a novel, cost-effective
mechanism to support shared-memory parallel applications that forgoes hardware maintained cache coherence. This mechanism
is based on the key ideas that mapping of lines to physical caches is done at the page level with OS support and that hardware
supports remote cache accesses. We extend our previous work by investigating in detail the impact of system design parameters
and extending the system to support multi-level cache hierarchies. Results show that the choice of implementation of multi-level
cache hierarchies can have a significant impact on performance. 相似文献
100.