A 1-V, 82-dB, 2.5-MS/s,single loop,single bit delta-sigma modulator in 0.13-μm CMOS technology

It is challenging to design high speed Delta-Sigma modulator using sub-micron process with low supply voltage. Compared with multi-stage or multi-bit design, the single loop, single bit Delta-Sigma modulator has relaxed requirement for the building blocks under low-voltage operation, which make it possible to get high conversion rate by increasing sampling frequency. In this study, a low voltage, high speed 4th-order Delta-Sigma modulator using input feed-forward is presented. Implemented with 0.13-μm CMOS technology and 1.0-V supply voltage, the discrete-time Delta-Sigma modulator achieves 2.5-MS/s conversion rate and 82-dB dynamic range, with the sampling frequency of 160-MHz and OSR of 64.     

A low-voltage low-power threshold voltage monitor for CMOS process sensing

In this paper a low-voltage low-power threshold voltage monitor for CMOS process sensing is presented. This circuit works in weak inversion and it can be used as an elementary circuit block for on-chip compensation of the intra-die or inter-die threshold voltage variations in low-power analog and mixed-signal SoC, since it is robust to temperature and power supply voltage variations (similar to the bandgap voltage reference). The proposed threshold voltage monitor has been successfully verified in a standard 0.35-μm n-well CMOS TSMC process. Experimental results have confirmed that the circuit generates an average reference voltage of 758 mV (very close to the typical threshold voltage when extrapolated to absolute zero) for a 950 mV power supply voltage, with a variation of 39 ppm/°C for the −20 to 80°C temperature range.     

Fast RSVP: Efficient RSVP Mobility Support for Mobile IPv6

In recent years, with the development of mobile communication technologies and the increase of available wireless transmission bandwidth, deploying multimedia services in next generation mobile IPv6 networks has become an inevitable trend. RSVP (resource reservation protocol) proposed by the IETF is designed for hardwired and fixed networks and can not be used in mobile environments. This paper proposes a protocol, called Fast RSVP, to reserve resources for mobile IPv6. The protocol adopts a cross-layer design approach where two modules (RSVP module and Mobile IPv6 module) at different layers cooperate with each other. Fast RSVP divides a handover process with QoS guarantees into two stages: (1) setup of the resource reservation neighbor tunnel and (2) resource reservation on the optimized route. It can help a mobile node realize fast handover with QoS guarantees as well as avoid resource wasting by triangular routes, advanced reservations and duplicate reservations. In addition, fast RSVP reserves “guard channels” for handover sessions, thus greatly reducing the handover session forced termination rate while maintaining high performance of the network. Based on extensive performance analysis and simulations, Fast RSVP, compared with existing methods of resource reservation in mobile environments, performs better in terms of packet delay and throughput during handover, QoS recovery time after handover, resource reservation cost, handover session forced termination rate and overall session completion rate.     

Cu Substrates with Different Grain Sizes

Cu₆Sn₅ and Cu₃Sn are easily formed at the interface between Sn and Cu during reflow and aging processes. Thick Cu-Sn compounds at the interface become brittle, reducing the mechanical strength of solder joints and increasing the consumption of under bump metallization (UBM). It is noted that intermetallic compound (IMC) growth and substrate consumption are affected by factors such as substrate fabrication, substrate orientation, and substrate microstructure. In this study, to determine the effects of substrate grain size on IMC growth and substrate consumption, pure Sn solder was reflowed on annealed Cu substrates with different grain sizes at 250°C for 30 s to 600 s. It was revealed that Cu substrates with smaller grain sizes exhibited reduced IMC growth. In addition, the interdiffusion coefficients of Cu₆Sn₅ and Cu₃Sn were decreased for the Cu substrate with the smaller grain size. The influence of the Cu substrate grain size on IMC growth and substrate consumption is discussed.     

Topological Patterns for Scalable Representation and Analysis of Dataflow Graphs

Tools for designing signal processing systems with their semantic foundation in dataflow modeling often use high-level graphical user interfaces (GUIs) or text based languages that allow specifying applications as directed graphs. Such graphical representations serve as an initial reference point for further analysis and optimizations that lead to platform-specific implementations. For large-scale applications, the underlying graphs often consist of smaller substructures that repeat multiple times. To enable more concise representation and direct analysis of such substructures in the context of high level DSP specification languages and design tools, we develop the modeling concept of topological patterns, and propose ways for supporting this concept in a high-level language. We augment the dataflow interchange format (DIF) language—a language for specifying DSP-oriented dataflow graphs—with constructs for supporting topological patterns, and we show how topological patterns can be effective in various aspects of embedded signal processing design flows using specific application examples.     

The Asymmetric Golden Code for Fast Decoding on Time-Varying Channels

The golden code is a full-rate full-diversity space–time code for the two-input two-output channel with good performance but high decoding complexity. The overlaid Alamouti codes were recently proposed as an alternative; in exchange for a slight performance penalty, they have lower decoding complexity on quasistatic channels with QAM alphabets. However, the complexity advantage of the overlaid codes vanishes for time-varying channels. This paper proposes the asymmetric golden code, a novel full-rate and full-diversity space–time code for the two-input two-output channel that offers reduced-complexity decoding on both quasistatic and time-varying channels.     

Analysis of Heuristic Graph Partitioning Methods for the Assignment of Packet Control Units in GERAN

Over the last few years, graph partitioning has been recognized as a suitable technique for optimizing cellular network structure. For example, in a recent paper, the authors proposed a classical graph partitioning algorithm to optimize the assignment of cells to Packet Control Units (PCUs) in GSM-EDGE Radio Access Network. Based on this approach, the quality of packet data services in a live environment was increased by reducing the number of cell re-selections between different PCUs. To learn more about the potential of graph partitioning in cellular networks, in this paper, a more sophisticated, yet computationally efficient, partitioning algorithm is proposed for the same problem. The new method combines multi-level refinement and adaptive multi-start techniques with algorithms to ensure the connectivity between cells under the same PCU. Performance assessment is based on an extensive set of graphs constructed with data taken from a live network. During the tests, the new method is compared with classical graph partitioning approaches. Results show that the proposed method outperforms classical approaches in terms of solution quality at the expense of a slight increase in computing time, while providing solutions that are easier to check by the network operator.     

Cognitive Radio Concept and Challenges in Dynamic Spectrum Access for the Future Generation Wireless Communication Systems

Recently, the Dynamic Spectrum Access (DSA) techniques are proposed to solve the problem of spectrum scarcity and help to use the limited spectrum resource as effectively as possible. The current ongoing spectrum reform opens up the possibilities to exploit the DSA techniques. This paper aims to provide a critical review on the various ongoing efforts towards the use of DSA concept for the frequency management of future wireless communications systems, especially from the Cognitive Radio (CR) perspective. The CR aims for an efficient and dynamic access to the spectrum, and provides a new method of spectrum management. This paper also highlights the various challenges associated with CR in order to realize the concept of DSA.     

Automatic Image Annotation Based on Generalized Relevance Models

This paper presents a generalized relevance model for automatic image annotation through learning the correlations between images and annotation keywords. Different from previous relevance models that can only propagate keywords from the training images to the test ones, the proposed model can perform extra keyword propagation among the test images. We also give a convergence analysis of the iterative algorithm inspired by the proposed model. Moreover, to estimate the joint probability of observing an image with possible annotation keywords, we define the inter-image relations through proposing a new spatial Markov kernel based on 2D Markov models. The main advantage of our spatial Markov kernel is that the intra-image context can be exploited for automatic image annotation, which is different from the traditional bag-of-words methods. Experiments on two standard image databases demonstrate that the proposed model outperforms the state-of-the-art annotation models.     

Instruction-Vulnerability-Factor-Based Reliability Analysis Model for Program Memory

Bit faults induced by single-event upsets in instruction may not cause a system to experience an error. The instruction vulnerability factor (IVF) is first defined to quantify the effect of non-effective upsets on program reliability in this paper; and the mean time to failure (MTTF) model of program memory is then derived based on IVF. Further analysis of MTTF model concludes that the MTTF of program memory using error correcting code (ECC) and scrubbing is not always better than unhardened program memory. The constraints that should be met upon utilizing ECC and scrubbing in program memory are presented for the first time, to the best of authors’ knowledge. Additionally, the proposed models and conclusions are validated by Monte Carlo simulations in MATLAB. These results show that the proposed models have a good accuracy and their margin of error is less than 3 % compared with MATLAB simulation results. It should be highlighted that our conclusions may be used to contribute to selecting the optimal fault-tolerant technique to harden the program memory.