Synthesis,characterization, and supercapacitor studies of manganese (IV) oxide nanowires

One-dimensional manganese (IV) oxide (MnO₂) (～20 nm in average diameter) were synthesized by cathodic electrodeposition and heat treatment. The mechanism of electrodeposition and nanowire formation were discussed. The product was characterized by X-ray diffraction (XRD), scanning electron microscopy (SEM), transmission electron microscopy (TEM) and Fourier transform infrared (FT-IR). Nanowires with varying lengths and diameters were found in TEM and SEM images of the sample. The results of N₂ adsorption–desorption analysis indicated that the BET surface area of the MnO₂ nanowires was 157 m² g^?1 and the pore size distributions were 2.5 and 4.5 nm. The electrochemical performances of the prepared MnO₂ as an electrode material for supercapacitors were evaluated by cyclic voltammetry and galvanostatic charge/discharge measurements in a solution of 0.5 M Na₂SO₄. The higher specific capacitance of 318 F g^?1 and good capacity retention of 86% were achieved after 1000 charge–discharge cycles had been observed for the MnO₂ nanowires electrode.     

A wide frequency range delay line for fast-locking and low power delay-locked-loops

A voltage controlled delay cell with wide frequency range is presented in this paper. The delay-line which is resulted by connecting five series of delay cells generating a wide range of delay from 1.9 to 13.24 ns. It can be used in an analog delay locked loop. The linear characteristic of the circuit with respect to the conventional delay line structures is improved, and a better performance of noise is obtained using differential structure. This circuit is designed by ADS software and TSMC CMOS 0.18 μm technology, with supply voltage 1.8 V. By changing control voltage from 0.335 to 1.8 V in delay line, a wide range of frequency from 75.52 to 917.43 MHz will be covered. Simulation results show that the proposed delay line has power consumption of maximum 3.77 mW at frequency of 75.52 MHz. It also shows that increasing of frequency will reduce power dissipation which is the one of the main characteristics of this novel circuit. Moreover, the delay locked loop which uses these delay cells has a very high lock speed so that the maximum lock time in just five clock cycles.     

Steady-state analysis of quantized distributed incremental LMS algorithm without Gaussian restriction

In this paper, we analyze the steady-state performance of the distributed incremental least mean-square (DILMS) algorithm when it is implemented in finite-precision arithmetic. Our analysis in this paper does not consider any distribution of input data. We first formulate the update equation for quantized DILMS algorithm, and then we use a spatial-temporal energy conservation argument to derive theoretical expressions that evaluate the steady-state performance of individual nodes in the network. We consider mean-square error, excess mean-square error, and mean-square deviation as the performance criteria. Simulation results are generated by using two types of signals, Gaussian and non-Gaussian distributed signals. As the simulation results show, there is a good match between the theory and simulation.     

Time-Domain Block and Per-Tone Equalization for MIMO–OFDM in Shallow Underwater Acoustic Communication

Shallow underwater acoustic (UWA) channel exhibits rapid temporal variations, extensive multipath spreads, and severe frequency-dependent attenuations. So, high data rate communication with high spectral efficiency in this challenging medium requires efficient system design. Multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO–OFDM) is a promising solution for reliable transmission over highly dispersive channels. In this paper, we study the equalization of shallow UWA channels when a MIMO–OFDM transmission scheme is used. We address simultaneously the long multipath spread and rapid temporal variations of the channel. These features lead to interblock interference (IBI) along with intercarrier interference (ICI), thereby degrading the system performance. We describe the underwater channel using a general basis expansion model (BEM), and propose time-domain block equalization techniques to jointly eliminate the IBI and ICI. The block equalizers are derived based on minimum mean-square error and zero-forcing criteria. We also develop a novel approach to design two time-domain per-tone equalizers, which minimize bit error rate or mean-square error in each subcarrier. We simulate a typical shallow UWA channel to demonstrate the desirable performance of the proposed equalization techniques in Rayleigh and Rician fading channels.     

Gas Diffusion,Energy Transport,and Thermal Accommodation in Single‐Walled Carbon Nanotube Aerogels

The thermal conductivity of gas‐permeated single‐walled carbon nanotube (SWCNT) aerogel (8 kg m^?3 density, 0.0061 volume fraction) is measured experimentally and modeled using mesoscale and atomistic simulations. Despite the high thermal conductivity of isolated SWCNTs, the thermal conductivity of the evacuated aerogel is 0.025 ± 0.010 W m^?1 K^?1 at a temperature of 300 K. This very low value is a result of the high porosity and the low interface thermal conductance at the tube–tube junctions (estimated as 12 pW K^?1). Thermal conductivity measurements and analysis of the gas‐permeated aerogel (H₂, He, Ne, N₂, and Ar) show that gas molecules transport energy over length scales hundreds of times larger than the diameters of the pores in the aerogel. It is hypothesized that inefficient energy exchange between gas molecules and SWCNTs gives the permeating molecules a memory of their prior collisions. Low gas‐SWCNT accommodation coefficients predicted by molecular dynamics simulations support this hypothesis. Amplified energy transport length scales resulting from low gas accommodation are a general feature of CNT‐based nanoporous materials.     

Efficient Computation Offloading Decision in Mobile Cloud Computing over 5G Network

Due to the significant advancement of Smartphone technology, the applications targeted for these devices are getting more and more complex and demanding of high power and resources. Mobile cloud computing (MCC) allows the Smart phones to perform these highly demanding tasks with the help of powerful cloud servers. However, to decide whether a given part of an application is cost-effective to execute in local mobile device or in the cloud server is a difficult problem in MCC. It is due to the trade-off between saving energy consumption while maintaining the strict latency requirements of applications. Currently, 5th generation mobile network (5G) is getting much attention, which can support increased network capacity, high data rate and low latency and can pave the way for solving the computation offloading problem in MCC. In this paper, we design an intelligent computation offloading system that takes tradeoff decisions for code offloading from a mobile device to cloud server over the 5G network. We develop a metric for tradeoff decision making that can maximize energy saving while maintain strict latency requirements of user applications in the 5G system. We evaluate the performances of the proposed system in a test-bed implementation, and the results show that it outperforms the state-of-the-art methods in terms of accuracy, computation and energy saving.     

Arbitrary dual-band unequal Wilkinson power divider based on negative refractive index transmission lines

This paper focused on the application of negative refractive index transmission line (NRI-TL) in dual-band unequal Wilkinson power divider (WPD) with controllable frequency and power dividing ratio. Theory and design procedure of the dual-band NRI-TL are presented in details. For demonstration, two dual-band unequal Wilkinson power dividers (WPDs) with power dividing ratio of 2 : 1 and operating frequencies of 0.9 and 1.8 GHz are designed, fabricated and tested. The first unequal divider is based on 2-stage NRI-TLs and the second one is based on 4-stage NRI-TLs. In addition, these two types of NRI-TLs are presented to demonstrate that by increasing the number of NRI-TL unit-cells the phase response of the NRI-TLs converge to the desired characteristic. The good agreement between measured and simulated results confirmed the design concept and derived closed-form design equations. Measurements show that the first divider has 18.37% and 21.86% relative bandwidths and the second one has 33.52% and 29.12% relative bandwidths at 0.9 and 1.8 GHz, respectively. The design concept of this paper can be extended to equal dual-band power dividers with arbitrary frequency ratio.     

Interpolation techniques for building a continuous map from discrete wireless sensor network data

Wireless sensor networks (WSNs) typically gather data at a discrete number of locations. However, it is desirable to be able to design applications and reason about the data in more abstract forms than in points of data. By bestowing the ability to predict inter‐node values upon the network, it is proposed that it will become possible to build applications that are unaware of the concrete reality of sparse data. This interpolation capability is realised as a service of the network. In this paper, the ‘map’ style of presentation has been identified as a suitable sense data visualisation format. Although map generation is essentially a problem of interpolation between points, a new WSN service, called the map generation service, which is based on a Shepard interpolation method, is presented. A modified Shepard method that aims to deal with the special characteristics of WSNs is proposed. It requires small storage, can be localised and integrates the information about the application domain to further reduce the map generation cost and improve the mapping accuracy. Empirical analysis has shown that the map generation service is an accurate, a flexible and an efficient method. Copyright © 2011 John Wiley & Sons, Ltd.     

A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes

A new parameterized-core-based design methodology targeted for programmable decoders for low-density parity-check (LDPC) codes is proposed. The methodology solves the two major drawbacks of excessive memory overhead and complex on-chip interconnect typical of existing decoder implementations which limit the scalability, degrade the error-correction capability, and restrict the domain of application of LDPC codes. Diverse memory and interconnect optimizations are performed at the code-design, decoding algorithm, decoder architecture, and physical layout levels, with the following features: (1) Architecture-aware (AA)-LDPC code design with embedded structural features that significantly reduce interconnect complexity, (2) faster and memory-efficient turbo-decoding algorithm for LDPC codes, (3) programmable architecture having distributed memory, parallel message processing units, and dynamic/scalable transport networks for routing messages, and (4) a parameterized macro-cell layout library implementing the main components of the architecture with scaling parameters that enable low-level transistor sizing and power-rail scaling for power-delay-area optimization. A 14.3 mm² programmable decoder core for a rate-1/2, length 2048 AA-LDPC code generated using the proposed methodology is presented, which delivers a throughput of 6.4 Gbps at 125 MHz and consumes 787 mW of power.Mohammad M. Mansour received his B.E. degree with distinction in 1996 and his M.S. degree in 1998 all in Computer and Communications Engineering from the American University of Beirut (AUB). In August 2002, he received his M.S. degree in Mathematics from the University of Illinois at Urbana-Champaign (UIUC). Mohammad received his Ph.D. in Electrical Engineering in May 2003 from UIUC. He is currently an Assistant Professor of Electrical Engineering with the ECE department at AUB. From 1998 to 2003, he was a research assistant at the Coordinated Science Laboratory (CSL) at UIUC. In 1997 he was a research assistant at the ECE department at AUB, and in 1996 he was a teaching assistant at the same department. From 1992–1996 he was on the Deans honor list at AUB. He received the Harriri Foundation award twice in 1996 and 1998, the Charli S. Korban award twice in 1996 and 1998, the Makhzoumi Foundation Award in 1998, and the PHI Kappa PHI Honor Society awards in 2000 and 2001. During the summer of 2000, he worked at National Semiconductor Corp., San Francisco, CA, with the wireless research group. His research interests are VLSI architectures and integrated circuit (IC) design for communications and coding theory applications, digital signal processing systems and general purpose computing systems.Naresh R. Shanbhag received the B.Tech from the Indian Institute of Technology, New Delhi, India, in 1988, M.S. from Wright State University and Ph.D. degree from the University of Minnesota, in 1993, all in Electrical Engineering. From July 1993 to August 1995, he worked at AT&T Bell Laboratories at Murray Hill in the Wide-Area Networks Group, where he was responsible of development of VLSI algorithms, architectures and implementation for high-speed data communications applications. In particular, he was the lead chip architect for AT&Ts 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and broadband access. Since August 1995, he is with the Department of Electrical and Computer Engineering, and the Coordinated Science Laboratory where he is presently an Associate Professor and Director of the Illinois Center for Integrated Microsystems. At University of Illinois, he founded the VLSI Information Processing Systems (ViPS) Group, whose charter is to explore issues related to low-power, high-performance, and reliable integrated circuit implementations of broadband communications and digital signal processing systems. He has published numerous journal articles/book chapters/conference publications in this area and holds three US patents. He is also a co-author of the research monograph Pipelined Adaptive Digital Filters (Norwell, MA: Kluwer, 1994). Dr. Shanbhag received the 2001 IEEE Transactions Best Paper Award, 1999 Xerox Faculty Research Award, 1999 IEEE Leon K. Kirchmayer Best Paper Award, the 1997 Distinguished Lecturer of IEEE Circuit and Systems Society (97–99), the National Science Foundation CAREER Award in 1996, and the 1994 Darlington Best Paper Award from the IEEE Circuits and Systems society. From 1997–99 and 2000–2002, he served as an Associate Editor for IEEE Transaction on Circuits and Systems: Part II and an Associate Editor for the IEEE Transactions on VLSI, respectively. He was the technical program chair for the 2002 IEEE Workshop on Signal Processing Systems (SiPS02).