A survey on nonlinear analog-to-digital converters

This paper presents a survey on Nonlinear Analog-to-Digital converters (ADC). This class of converters is extremely relevant in applications where there is a need for non-uniform quantization characteristic, for example, some specific applications in the areas of light detection, hearing aid, nuclear physics, image acquisition, communication systems, etc. This survey outlines the state-of-the-art Nonlinear ADC topologies, such as, floating point, logarithmic, piecewise linear and oversampled nonlinear converters, and discusses their performance and advantages in terms of their applications.     

Scalable Data Processing for Community Sensing Applications

Participatory Sensing is a new computing paradigm that aims to turn personal mobile devices into advanced mobile sensing networks. For popular applications, we can expect a huge number of users to both contribute with sensor data and request information from the system. In such scenario, scalability of data processing becomes a major issue. In this paper, we present a system for supporting participatory sensing applications that leverages cluster or cloud infrastructures to provide a scalable data processing infrastructure. We propose and evaluate three strategies for data processing in this architecture.     

Analog circuits optimization based on evolutionary computation techniques

This paper presents a new design automation tool, based on a modified genetic algorithm kernel, in order to improve efficiency on the analog IC design cycle. The proposed approach combines a robust optimization with corner analysis, machine learning techniques and distributed processing capability able to deal with multi-objective and constrained optimization problems. The resulting optimization tool and the improvement in design productivity is demonstrated for the design of CMOS operational amplifiers.     

Automatic Synthesis of Motion Estimation Processors Based on a New Class of Hardware Architectures

A new class of fully parameterizable multiple array architectures for motion estimation in video sequences based on the Full-Search Block-Matching algorithm is proposed in this paper. This class is based on a new and efficient AB2 single array architecture with minimum latency, maximum throughput and full utilization of the hardware resources. It provides the ability to configure the target processor within the boundary values imposed for the configuration parameters concerning the algorithm setup, the processing time and the circuit area. With this purpose, a software configuration tool has been implemented to determine the set of possible configurations which fulfill the requisites of a given video coder. Experimental results using both FPGA and ASIC technologies are presented. In particular, the implementation of a single array processor configuration on a single-chip is illustrated, evidencing the ability to estimate motion vectors in real-time.     

A Low-Power Wakeup Radio for Application in WSN-Based Indoor Location Systems

This paper presents a low-power wakeup radio (WUR) for application in indoor location systems. The presented radio has a better performance than the state-of-the-art radios, since it has low-power consumption, only 10 μW and it is perfectly integrated into a wireless sensor network based on ZigBee, which is used for location purposes. This performance was achieved due to an optimised radio frequency design of the WUR, which was embedded with a low-cost/low-power processor, and due to an enhanced control algorithm. Moreover, a software defined radio approach has been used to implement the WUR protocol. The WUR was designed and integrated in an existing WSN-based indoor location system which was originally based on a periodic sleep-wake up duty-cycled protocol. In the WUR protocol the location sensor is kept in deep sleep mode until it receives an external wake-up order. According to estimates, with this scheme, the battery lifetime can be increased from 200 days (using conventional duty-cycle protocol) up to almost 8000 days (sensor waken-up few times per day).     

A bi-criteria minimum spanning tree routing model for MPLS/overlay networks

The MPLS platform enables the implementation of advanced multipath and multicast routing schemes. This work develops and analyses the performance of a new bi-criteria minimum spanning tree model intended for routing broadcast messages in MPLS networks or constructing tree-based overlay networks. The aim of the model is to obtain spanning trees which are compromise solutions with respect to two important traffic engineering metrics: load balancing cost and average delay bound. An exact solution to the formulated bi-criteria optimization problem is presented, which is based on an algorithm that enables the computation of the set of supported non-dominated spanning trees. An application model and a set of experiments on randomly generated Internet type topologies will also be presented. Finally a network performance analysis of the model considering three network performance metrics will be shown.     

Recyclable,Flexible, Low‐Power Oxide Electronics

The ability to process and dimensionally scale field‐effect transistors with and on paper and to integrate them as a core component for low‐power‐consumption analog and digital circuits is demonstrated. Low‐temperature‐processed p‐ and n‐channel integrated oxide thin‐film transistors in the complementary metal oxide semiconductor (CMOS) inverter architecture are seamlessly layered on mechanically flexible, low‐cost, recyclable paper substrates. The possibility of building these circuits using low‐temperature processes opens the door to new applications ranging from smart labels and sensors on clothing and packaging to electronic displays printed on paper pages for use in newspapers, magazines, books, signs, and advertising billboards. Because the CMOS circuits reported constitute fundamental building blocks for analog and digital electronics, this development creates the potential to have flexible form factor computers seamlessly layered onto paper. The holistic approach of merging low‐power circuitry with a recyclable substrate is an important step towards greener electronics.     

Giant Anomalous Hall and Nernst Conductivities in Magnetic All-d Metal Heusler Alloys

All-d Heuslers are a category of novel compounds combining versatile functionalities such as caloric responses and spintronics with enhanced mechanical properties. Despite the promising transport properties (anomalous Hall (AHC) and anomalous Nernst (ANC) conductivities) shown in the conventional Co₂XY Heuslers with p-d hybridization, the all-d Heuslers with only d-d hybridization open a new horizon to search for new candidates with outstanding transport properties. In this work, the AHC and ANC are evaluated for thermodynamically stable ferro/ferri-magnetic all-d-metal regular Heusler compounds based on high-throughput first-principles calculations. It is observed that quite a few materials exhibit giant AHCs and ANCs, such as cubic Re₂TaMn with an AHC of 2011 S cm^-1, and tetragonal Pt₂CrRh with an AHC of 1966 S cm^-1 and an ANC of 7.50 A m^-1K^-1. Comprehensive analysis on the electronic structure reveals that the high AHC can be attributed to the occurrence of the Weyl nodes or gapped nodal lines in the neighborhood of the Fermi level. The correlations between such transport properties and the number of valence electrons are also thoroughly investigated, which provides a practical guidance to tailor AHC and ANC via chemical doping for transverse thermoelectric applications.