Understanding and Predicting Data Hotspots in Cellular Networks

The unprecedented growth in mobile data usage is posing significant challenges to cellular operators. One key challenge is how to provide quality of service to subscribers when their residing cell is experiencing a significant amount of traffic, i.e. becoming a traffic hotspot. In this paper, we perform an empirical study on data hotspots in today’s cellular networks using a 9-week cellular dataset with 734K+ users and 5327 cell sites. Our analysis examines in details static and dynamic characteristics, predictability, and causes of data hotspots, and their correlation with call hotspots. We show that using standard machine learning methods, future hotspots can be accurately predicted from past observations. We believe the understanding of these key issues will lead to more efficient and responsive resource management and thus better QoS provision in cellular networks. To the best of our knowledge, our work is the first to empirically characterize traffic hotspots in today’s cellular networks.     

Analysis of three-dimensional turbo codes

Our paper presents a detailed study of the three-dimensional turbo code (3D TC). This code which combines both parallel and serial concatenation is derived from the classical TC by concatenating a rate-1 post-encoder at its output. The 3D TC provides very low error rates for a wide range of block lengths and coding rates, at the expense of an increase in complexity and a loss in convergence. This paper deals with the performance improvement of the 3D TC. First, we optimize the distance spectrum of the 3D TC by means of the adoption of a non regular post-encoding pattern. This allows us to increase the minimum hamming distance (MHD) and thereby to improve the performance at very low error rates. Then, we propose a time varying construction of the post-encoded parity in order to reduce the observable loss of convergence at high error rates. Performance comparisons are made between the 3GPP2 standardized TC and the corresponding 3D code. The different improvement stages are illustrated with simulation results, asymptotical bounds, and EXIT charts.     

Link budget analysis for multistandard receiver architectures

As devices shrink, creating integrated circuits (ICs) that work with the required accuracy becomes more difficult due to issues related to device physics. Receivers are part of an area referred to as "mixed-signal design," meaning that both analog and digital circuitry will be on the same IC. This too presents many challenging issues, as the analog circuitry is highly sensitive to disruptions caused by the noisy digital circuitry. Therefore, accurate modeling and simulation is crucial in the design of wireless receivers to ensure the best possible operation of the fabricated IC. Through simulation and modeling a designer can determine if receiver architecture will meet the required specifications and pinpoint the possible problems before valuable time is spent developing the actual circuit. This article will present design issues for multistandard wireless receivers to give the reader an understanding of the challenges involved in link-budget analysis. TITAN (Toolbox for Integrated Transceiver Analysis), a link-budget analysis tool developed at The Ohio State University Analog VLSI Laboratory, will be presented as an example of a tool for receiver simulation. To determine design performance, various requirements must be translated to model parameters. Among the requirements for receivers are noise floor (NF), second- and third-order distortion (IP2 and IP3, respectively), reciprocal mixing, and phase noise. TITAN offers a graphical interface and encapsulated models to the designer, eliminating the possibility of formula corruption. The interface provides a more intuitive and sophisticated way of setting up the simulation and provides the designer with more readable results. Additionally, a blocking profile component allows the architecture to be tested across multiple standards.     

Radio resource management for LTE-A relay-enhanced cells with spatial reuse and max–min fairness

One of the major issues in LTE-Advanced (LTE-A) systems is the poor capacity at the cell edge. This is mainly due to the interference experienced by the users as a result of the aggressive frequency reuse usually implemented. Relaying offers an attractive solution for this problem by offering better links than those with the eNodeB (eNB) for the terminals suffering from high path loss or high interference. However, adding relays complicates the resource allocation problem at the eNB and therefore the need for more efficient schemes arises. This is also aggravated by the reuse of resource blocks (RBs) by the relays to fully exploit the scarce spectrum, which, in turn, leads to intra-cell interference. In this paper, we study the joint power and resource allocation problem in LTE-A relay-enhanced cells that exploit spatial reuse. To guarantee fairness among users, a max–min fair optimization objective is used. This complex problem is solved using coordinate ascent and the difference of two convex functions (DC) programming techniques and the proposed scheme indeed converges to a local-optimum quickly. This is shown to be a satisfactory solution according to the simulation results that indicate an almost sevenfold increase in the 10th percentile capacity when compared to previously proposed solutions.     

A single-stage zero-voltage zero-current-switched full-bridge DCpower supply with extended load power range

A single-stage power-factor-corrected pulsewidth modulation power converter with extended load power range is presented. The topology is based on a zero-voltage zero-current-switched full-bridge (ZVZCS-FB) inverter. Steady-state analysis of the topology shows that by operating the LC load filter in discontinuous mode, the DC-link voltage remains bounded and independent of the load level. Therefore, the load power range can be further expanded, including the no-load operating condition. The analysis also shows that the extension of the load power range is achieved without any penalty in: (1) the input power factor (due to the input current waveshaping feature); (2) the power converter efficiency (due to ZVZCS and the single-stage features); and (3) the load voltage quality (due to the high bandwidth of the phase control loop). Simulated and experimental results are included to show the feasibility of the proposed scheme     

Investigation of pillar thickness variation effect on oblique rotating implantation (ORI)-based vertical double gate MOSFET

The rapid scaling of integrated circuit requires further shrinkage of lateral device dimension, which correlates with pillar thickness in vertical structure. This paper investigates the effect of pillar thickness variation on vertical double gate MOSFET (VDGM) fabricated using oblique rotating ion implantation (ORI) method. For this purpose, several scenarios of silicon pillar thickness t_si were evaluated for 20–100 nm channel length. The source region was found to merge at pillar thickness below 75 nm, which results in floating body effect and creates isolated region in the middle of pillar. The vertical devices using ORI method show better performance than those with conventional implantation method for all pillar thickness, due to the elimination of corner effect that degrades the gate control. The presence of isolated depletion region in the middle of pillar at floating body increases parasitic effect for higher drain potential. By further reduction of pillar thickness towards fully depleted feature, the increase in gate-to gate charge coupling improves the performance of ORI-based vertical double gate MOSFET, as evident in near-ideal swing value and lower DIBL, compared to the partially depleted and body-tied device.     

CMOS low-voltage class-AB operational transconductance amplifier

The authors present a new low-voltage class-AB operational transconductance amplifier (OTA). The proposed OTA achieves a fast non slew-rate limited settling time with low power consumption. The circuit is power efficient when driving large capacitive loads. The OTA circuit is well suited for low-voltage low-power switched capacitor applications. Experimental results of the proposed circuit are included     

A CMOS highly linear channel-select filter for 3G multistandardintegrated wireless receivers

A new approach for designing digitally programmable CMOS integrated baseband filters is presented. The proposed technique provides a systematic method for designing filters exhibiting high linearity and low power. A sixth-order Butterworth low-pass filter with 14-bit bandwidth tuning range is designed for implementing the baseband channel-select filter in an integrated multistandard wireless receiver. The filter consumes a current of 2.25 mA from a 2.7-V supply and occupies an area of 1.25 mm² in a 0.5-μm chip. The proposed filter design achieves high spurious free dynamic ranges (SFDRs) of 92 dB for PDC (IS-54), 89 dB for GSM, 84 dB for IS-95, and 80 dB for WCDMA     

Statistical Design of the Four-MOSFET Structure

The statistical design of the four-MOSFET structure is presented in this paper. The quantitative measure of the effect of mismatch between the four transistors on nonlinearity and offset current is provided through contours. Statistical optimization of the transistor and values is demonstrated. The four-MOSFET structure was fabricated through the MOSIS 2 m process using MOS transistor Level-3 model parameters. Experimental results are included in the paper.