Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).     

2-D symmetry: theory and filter design applications

In this comprehensive review article, we present the theory of symmetry in two-dimensional (2-D) filter functions and in 2-D Fourier transforms. It is shown that when a filter frequency response possesses symmetry, the realization problem becomes relatively simple. Further, when the frequency response has no symmetry, there is a technique to decompose that frequency response into components each of which has the desired symmetry. This again reduces the complexity of two-dimensional filter design. A number of filter design examples are illustrated.     

Effect of anisotropy of tin on thermomechanical behavior of solder joints

Properties of body centered tetragonal tin are highly anisotropic. As a consequence large stresses can develop at the tin grain boundaries due to coefficient of thermal expansion mismatch during temperature excursions. A modeling approach to evaluate the 3D stress states that develop at grain boundaries during thermomechanical fatigue in tin-based solder is presented. Development of significant amounts of stresses in the plane of the grain boundary can cause grain-boundary sliding and surface-relief effects, while those normal to the grain boundary can cause grain-boundary decohesion and cracking.     

The effects of nonlocal impact ionization on the speed of avalanche photodiodes

The nonlocal enhancement in the velocities of charge carriers to ionization is shown to outweigh the opposing effects of dead space, increasing the avalanche speed of short avalanche photodiodes (APDs) over the predictions of a conventional local model which ignores both of these effects. The trends in the measured gain-bandwidth product of two short InAlAs APDs reported in the literature support this result. Relatively large speed benefits are predicted to result from further small reductions in the lengths of short multiplication regions.     

Inside Front Cover: The Elastic Properties and Plastic Behavior of Two‐Dimensional Polymer Structures Fabricated by Laser Interference Lithography (Adv. Funct. Mater. 10/2006)

The probing of the micromechanical properties within a two‐dimensional polymer structure with sixfold symmetry fabricated via interference lithography reveals a nonuniform spatial distribution in the elastic modulus “imprinted” with an interference pattern in work reported by Tsukruk, Thomas, and co‐workers on p. 1324. The image prepared by M. Lemieux and T. Gorishnyy shows how the interference pattern is formed by three laser beams and is transferred to the solid polymer structure. The elastic and plastic properties within a two‐dimensional polymer (SU8) structure with sixfold symmetry fabricated via interference lithography are presented. There is a nonuniform spatial distribution in the elastic modulus, with a higher elastic modulus obtained for nodes (brightest regions in the laser interference pattern) and a lower elastic modulus for beams (darkest regions in the laser interference pattern) of the photopatterned films. We suggest that such a nonuniformity and unusual plastic behavior are related to the variable material properties “imprinted” by the interference pattern.     

Design procedure of class-E amplifier for off-nominal operation at 50% duty ratio

Design equations for satisfying the off-nominal operating condition [i.e., only the zero-voltage switching (ZVS) condition] of the Class-E amplifier with a linear shunt capacitance at a duty ratio D=0.5 are derived. A new parameter s (V/s), called the slope of switch voltage when the switch turns on is introduced to obtain an image of the distance from the nominal conditions. By examining off-nominal Class-E operation degree of the design freedom of the Class-E amplifier increases by one. In addition various amplifier parameters such as operating frequency, output power, and load resistance range can be set as design specifications. For example, the peak switch voltage and switch current can be taken into account in the design procedure. Examples of a design procedure of the Class-E amplifier for off-nominal operation are given. The theoretical results were verified with PSpice simulation and experiments.     

Curie Temperatures of III–V Diluted Magnetic Semiconductors Calculated from First-Principles in Mean Field Approximation

Electronic structure and ferromagnetism in III–V compound-based diluted magnetic semiconductors (DMS) are investigated based on first-principles calculations by using the Korringa-Kohn-Rostoker method combined with the coherent-potential-approximation. The stability of the ferromagnetic phase in GaN-, GaAs-, GaP-, GaSb-based DMS is investigated systematically. The calculations show that 3d-impurities from the first-half of the transition metal series favor the ferromagnetic state, while impurities from the latter-half of the series exhibit spin-glass behavior. This chemical trend in the magnetism is explained by the double exchange mechanism taking the local symmetry at the impurity gap states into account. Curie temperatures of GaAs- and GaN-based DMS are estimated by using the Heisenberg model in a mean field approximation with the parameters calculated from first-principles. It is suggested that room-temperature ferromagnetism can be realized in these systems.     

A CMOS multichannel 10-Gb/s transceiver

We describe a CMOS multichannel transceiver that transmits and receives 10 Gb/s per channel over balanced copper media. The transceiver consists of two identical 10-Gb/s modules. Each module operates off a single 1.2-V supply and has a single 5-GHz phase-locked loop to supply a reference clock to two transmitter (Tx) channels and two receiver (Rx) channels. To track the input-signal phase, the Rx channel has a clock recovery unit (CRU), which uses a phase-interpolator-based timing generator and digital loop filter. The CRU can adjust the recovered clock phase with a resolution of 1.56 ps. Two sets of two-channel transceiver units were fabricated in 0.11-/spl mu/m CMOS on a single test chip. The transceiver unit size was 1.6 mm /spl times/ 2.6 mm. The Rx sensitivity was 120-mVp-p differential with a 70-ps phase margin for a common-mode voltage ranging from 0.6 to 1.0 V. The evaluated jitter tolerance curve met the OC-192 specification.     

High-performance self-aligned SiGeC HBT with selectively grown Si/sub 1-x-y/Ge/sub x/C/sub y/ base by UHV/CVD

Si/sub 1-x-y/Ge/sub x/C/sub y/ selective epitaxial growth (SEG) was performed by cold-wall, ultrahigh-vacuum chemical vapor deposition, and the effects of incorporating C on the crystallinity of Si/sub 1-x-y/Ge/sub x/C/sub y/ layers and the performance of a self-aligned SiGeC heterojunction bipolar transistor (HBT) were evaluated. A Si/sub 1-x-y/Ge/sub x/C/sub y/ layer with good crystallinity was obtained by optimizing the growth conditions. Device performance was significantly improved by incorporating C, as a result of applying Si/sub 1-x-y/Ge/sub x/C/sub y/ SEG to form the base of a self-aligned HBT. Fluctuations in device performance were suppressed by alleviating the lattice strain. Furthermore, since the B out diffusion could be suppressed by incorporating C, the cutoff frequency was able to be increased with almost the same base resistance. A maximum oscillation frequency of 174 GHz and an emitter coupled logic gate-delay time of 5.65 ps were obtained at a C content of 0.4%, which shows promise for future ultrahigh-speed communication systems.