Enhanced distributed explicit rate allocation for ABR services inATM networks

Rate allocation for available bit-rate (ABR) services in ATM networks has received a considerable amount of attention, but important issues such as bandwidth fairness, MCR rate guarantees, and queue control still require further investigation. In light of these concerns, an enhanced rate allocation algorithm is proposed for congestion management using explicit rate feedback control. The algorithm uses fast, exact rate computations and is capable of achieving a variety of MCR-related fairness criteria. The scheme handles transient effects and can function in heterogeneous networks carrying higher priority real-time traffic. Simulation results for a wide range of network scenarios demonstrate that the algorithm effectively controls queue buildups and achieves good fairness. Performance scalability to large networks under challenging conditions is also shown for a given control parameter set     

Three-dimensional discrete wavelet transform architectures

The three-dimensional (3-D) discrete wavelet transform (DWT) suits compression applications well, allowing for better compression on 3-D data as compared with two-dimensional (2-D) methods. This paper describes two architectures for the 3-D DWT, called the 3DW-I and the 3DW-II. The first architecture (3DW-I) is based on folding, whereas the 3DW-II architecture is block-based. Potential applications for these architectures include high definition television (HDTV) and medical data compression, such as magnetic resonance imaging (MRI). The 3DW-I architecture is an implementation of the 3-D DWT similar to folded 1-D and 2-D designs. It allows even distribution of the processing load onto 3 sets of filters, with each set performing the calculations for one dimension. The control for this design is very simple, since the data are operated on in a row-column-slice fashion. Due to pipelining, all filters are utilized 100% of the time, except for the start up and wind-down times. The 3DW-II architecture uses block inputs to reduce the requirement of on-chip memory. It has a central control unit to select which coefficients to pass on to the lowpass and highpass filters. The memory on the chip will be small compared with the input size since it depends solely on the filter sizes. The 3DW-I and 3DW-II architectures are compared according to memory requirements, number of clock cycles, and processing of frames per second. The two architectures described are the first 3-D DWT architectures     

A novel low-latency DRAM based on the bitline-discharge rate

As well known by computer architects, the performance gap between the processor and the memory has been increasing over the years. This causes what is known as the memory wall. In order to alleviate the problem, a novel fast readout scheme is proposed in this article for the single-transistor single-capacitor dynamic random-access memory (1T-1C DRAM) cells. The proposed scheme works in the current domain in which the difference between the discharging rates of the bitline in the cases of ‘1’ and ‘0’ readings is detected. The proposed scheme is analysed quantitatively and compared with the conventional readout scheme. It is verified by simulation adopting the 45 nm CMOS Berkley predictive-technology model (BPTM) and shows 44 and 7.7% reductions in the average read-access and cycle times, respectively, as compared to the conventional readout scheme. It is also shown that the power is saved according to the proposed scheme if the probability of occurrence of ‘0’ storage exceeds 66.7%. This minimum value can be alleviated, however, at the expense of a smaller saving in the average read-access time. The impacts of process variations and technology scaling are also taken into account.     

Security and key management in IoT‐based wireless sensor networks: An authentication protocol using symmetric key

Wireless sensor networks (WSN) consist of hundreds of miniature sensor nodes to sense various events in the surrounding environment and report back to the base station. Sensor networks are at the base of internet of things (IoT) and smart computing applications where a function is performed as a result of sensed event or information. However, in resource‐limited WSN authenticating a remote user is a vital security concern. Recently, researchers put forth various authentication protocols to address different security issues. Gope et al presented a protocol claiming resistance against known attacks. A thorough analysis of their protocol shows that it is vulnerable to user traceability, stolen verifier, and denial of service (DoS) attacks. In this article, an enhanced symmetric key‐based authentication protocol for IoT‐based WSN has been presented. The proposed protocol has the ability to counter user traceability, stolen verifier, and DoS attacks. Furthermore, the proposed protocol has been simulated and verified using Proverif and BAN logic. The proposed protocol has the same communication cost as the baseline protocol; however, in computation cost, it has 52.63% efficiency as compared with the baseline protocol.     

Sputtered metal lift-off for grating fabrication on InP based optical devices

Sputtered metal gratings have been realized using lift-off process based on bilayer resist electron beam lithography (EBL). The lithography mask is composed of PMMA (poly(methylméthacrylate)) layer deposited under HSQ (hydrogen silsesquioxane) inorganic resist. EBL is performed in HSQ, whereas PMMA is used to ease final lift-off. We demonstrate the possibility of patterning by lift-off metals with different sputtering yields and deposition conditions. Gratings with period of 200 nm and filling factor of 50% are obtained.     

Connection Management Protocols for Dynamic Lightpath Provisioning in Future WDM Networks

This paper investigates and compares the performance of two GMPLS-based distributed control and management protocols for dynamic lightpath provisioning in future IP networks. The first protocol is a global information-based link state approach that consists of both an integrated RWA algorithm and a signaling algorithm. Two triggering mechanisms for the LSAs update procedures are considered; one is periodic-based and the other is threshold-based. The second protocol is a local-information based fixed alternate link routing approach where the signaling protocol is closely integrated with the RWA protocols.     

A Dempster–Shafer Based Tit-for-Tat Strategy to Regulate the Cooperation in VANET Using QoS-OLSR Protocol

In this paper, we address the problem of cooperation among vehicles in VANET using QoS-OLSR protocol in the presence of selfish nodes. QoS-OLSR is a proactive protocol that considers the Quality of Service (QoS) of the nodes while electing the cluster-heads and selecting the Multi-Point Relay (MPRs) nodes. Cluster-heads and MPRs might misbehave on the roads by over-speeding or under-speeding. Classical and generous Tit-for-Tats are proposed to analyze the interaction among vehicles. However, both strategies are not able to enforce the cooperation due the fact that they (1) count on individual watchdogs monitoring, (2) rely on the node-to-node cooperation decision, (3) and ignore the high mobility and packet collisions. Therefore, we propose a Dempster–Shafer based Tit-for-Tat strategy that is able to improve the decision and regulate the cooperation in the vehicular network. This is done by (1) launching a cooperative watchdogs monitoring, (2) correlating the observations of the different watchdogs using Dempster–Shafer theory, and (3) propagating the decisions among clusters. Thereafter, we compare the Dempster–Shafer based strategy with several strategies derived from the original Tit-for-Tat. Simulation results prove that the Dempster–Shafer based strategy is able to maintain the survivability of the vehicular network in the presence of high mobility and packet collisions with minimal time and overhead.     

Performance analysis of low-power 1-bit CMOS full adder cells

A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized into smaller modules. The modules are studied and evaluated extensively. Several designs of each of them are developed, prototyped, simulated and analyzed. Twenty different 1-bit full-adder cells are constructed (most of them are novel circuits) by connecting combinations of different designs of these modules. Each of these cells exhibits different power consumption, speed, area, and driving capability figures. Two realistic circuit structures that include adder cells are used for simulation. A library of full-adder cells is developed and presented to the circuit designers to pick the full-adder cell that satisfies their specific applications     

Optimal throughput performance in full-duplex relay assisted cognitive networks

Wireless Networks - In this paper, we study a full-duplex cooperative cognitive radio network with multiple full-duplex secondary users acting as potential relays for transmitting the packets of a...