FATIGUE DAMAGE IN 1045 STEEL UNDER VARIABLE AMPLITUDE BIAXIAL LOADING

Abstract— During constant amplitude loading, two different types of crack systems have been reported In the high cycle fatigue (HCF) region, cracks nucleate on a small number of maxium shear strain amplitude planes One of these cracks becomes a dominant crack and leads to failure of the specimen In the low cycle fatigue (LCF) region, equally developed microcracks are observed over the entire gage section and grow during the majority of the life. The failure is due to a linking in which the microcracks join up during the last few cycles of the fatigue life.
To investigate the interaction of these two types of crack systems in biaxial fatigue, experiments were performed on thin-wall tubular specimens in tension, torsion and combined tension-torsion loading The test program included step loading and block loading in which two equivalent strain amplitudes were employed. One of the equivalent strain amplitudes is in the HCF region and the other was in the LCF region
Fatigue lives were predicted from constant amplitude damage curves when a single crack system dominated the fatigue process Two competitive crack systems were sometimes developed on the maximum shear strain amplitude planes in a single specimen under block loading This resulted in a conservative prediction of the fatigue life.     

Specification methods for material-handling control algorithms in flexible manufacturing systems

Good methods are needed to specify, test, and debug material-handling control logic. This article surveys a number of representative methods for defining and describing control algorithms for programmable material-handling equipment used in flexible manufacturing systems. The methods are evaluated with regard to their suitability for communication between people and as bases for interfaces to automatic program generators. It is concluded that no single method is entirely satisfactory. Three methods (position diagrams, function block diagrams, and operation networks) have potential to be combined into an effective hybrid approach that minimizes the need for the user to switch between various conceptual models.     

Uncooled DBR laser directly Modulated at 3.125 gb/s as athermal transmitter for low-cost WDM systems

An uncooled three-section tunable distributed Bragg reflector laser is demonstrated as an athermal transmitter for low-cost uncooled wavelength-division-multiplexing (WDM) systems with tight channel spacing. A /spl plusmn/0.02-nm thermal wavelength drift is achieved under continuous-wave operation up to 70/spl deg/C. Dynamic sidemode suppression ratio of greater than 35 dB is consistently obtained under 3.125-Gb/s direct modulation over a 20/spl deg/C-70/spl deg/C temperature range, with wavelength variation of as low as /spl plusmn/0.2 nm. This indicates that more than an order of magnitude reduction in coarse WDM channel spacing is possible using this source.     

Waveband-switchable SOA ring laser constructed with a phase modulator loop mirror filter

An electrically tunable multiwavelength source has been developed using a birefringence-based optical comb filter in a semiconductor optical amplifier ring laser. The filter is constructed with an electrooptic phase modulator placed inside a fiber loop mirror. By controlling the birefringence of the modulator through the applied bias, the radio-frequency power, or the modulation frequency, we achieve a continuous shift of the spectral comb to access different interleaved wavebands. Electrical waveband switching has been successfully demonstrated for 21 wavelengths at 100-GHz grid spacing with an optical signal-to-noise ratio over 40 dB.     

Widely tunable bottom-emitting vertical-cavity SOAs

We present bottom-emitting tunable vertical-cavity semiconductor optical amplifiers (VCSOAs) with an effective wavelength tuning range of >20 nm. These devices utilize a high reflectivity micromechanically tunable Bragg mirror as the back reflector. Compared with our first generation tunable VCSOAs, the bottom-emitting devices exhibit a two-fold increase in the effective tuning range as well as a five-fold reduction in the required tuning voltage.     

Novel T-rail electrodes for substrate removed low-voltage high-speed GaAs/AlGaAs electrooptic modulators

A novel traveling-wave electrode utilizing capacitively loaded T-rail elements was developed for low-voltage high-speed substrate-removed GaAs/AlGaAs electrooptic modulators. Electrodes with varying dimensions were fabricated and characterized. Electrode phase velocity, characteristic impedance, loss coefficient, and capacitive loading were extracted from the measured s-parameters up to 40 GHz. Electrode was also simulated using a finite-element solver. The measured and calculated electrode capacitance values were found to be in excellent agreement, showing that the electrode can be precisely designed. Approaches were outlined to provide a group velocity-matched very high-speed modulator electrode suitable for a low drive-voltage substrate-removed GaAs/AlGaAs electro-optic modulator     

VLSI Implementation of Forward Error Control Technique for ATM Networks

In asynchronous transfer mode (ATM) networks, fixed length cells of 53 bytes are transmitted. A cell may be discarded during transmission due to buffer overflow or a detection of errors. Cell discarding seriously degrades transmission quality. The quality degradation can be reduced by employing efficient forward error control (FEC) to recover discarded cells. In this paper, we present the design and implementation of decoding equipment for FEC in ATM networks based on a single parity check (SPC) product code using very‐large‐scale integration (VLSI) technology. FEC allows the destination to reconstruct missing data cells by using redundant parity cells that the source adds to each block of data cells. The functionality of the design has been tested using the Model Sim 5.7cXE Simulation Package. The design has been implemented for a 5 ° 5 matrix of data cells in a Virtex‐E XCV 3200E FG1156 device. The simulation and synthesis results show that the decoding function can be completed in 81 clock cycles with an optimum clock of 56.8 MHz. A test bench was written to study the performance of the decoder, and the results are presented.     

Low-Power VLSI Implementation of the Inner Receiver for OFDM-Based WLAN Systems

In this paper, we propose low-power designs for the synchronizer and channel estimator units of the Inner Receiver in wireless local area network systems. The objective of the work is the optimization, with respect to power, area, and latency, of both the signal processing algorithms themselves and their implementation. Novel circuit design strategies have been employed to realize optimal hardware and power efficient architectures for the fast Fourier transform, arc tangent computation unit, numerically controlled oscillator, and the decimation filters. The use of multiple clock domains and clock gating reduces the power consumption further. These blocks have been integrated into an experimental digital baseband processor for the IEEE 802.11a standard implemented in the 0.25mum- 5-metal layer BiCMOS technology from Institute for High Performance Microelectronics.