The equivalent transmission-path model-a tool for analyzing errorfloor characteristics due to intersymbol interference in Nakagami-Ricefading environments

Land mobile radio systems such as car telephones and handy personal terminals used outdoors have enjoyed a remarkable evolution. To design reliable mobile radio systems, however, it is vital to have a good understanding of the impact of wave propagation characteristics on digital transmission quality in a wide variety of mobile radio environments. A very simple but general scheme for calculating irreducible bit error rate (BER) (namely, BER floor) due to intersymbol interference in frequency-selective Nakagami-Rice fading environments has been developed. The scheme, which we call the equivalent transmission-path model, plays a role in connecting wave propagation with digital transmission characteristics in a general manner. Through computer simulations assuming various types of delay profiles, we first identify key parameters of Nakagami-Rice fading dominating principally the occurrence of irreducible errors and we develop a simple method for the calculation of irreducible BER utilizing the nature or the key parameters. Then we examine the accuracy of the scheme for various types of phase-shift keying (PSK) transmission systems. Finally, based on the scheme, we show calculation examples of BER floor characteristics in line-of-sight fading environments     

A side-wall transfer-transistor cell (SWATT cell) for highlyreliable multi-level NAND EEPROMs

A multi-level NAND Flash memory cell, using a new Side-WAll Transfer-Transistor (SWATT) structure, has been developed for a high performance and low bit cost Flash EEPROM. With the SWATT cell, a relatively wide threshold voltage (V_th) distribution of about 1.1 V is sufficient for a 4-level memory cell in contrast to a narrow 0.6 V distribution that is required for a conventional 4-level NAND cell. The key technology that allows this wide V_th distribution is the Transfer Transistor which is located at the side wall of the Shallow Trench Isolation (STI) region and is connected in parallel with the floating gate transistor. During read, the Transfer Transistors of the unselected cells (connected in series with the selected cell) function as pass transistors. So, even if the V_th of the unselected floating gate transistor is higher than the control gate voltage, the unselected cell will be in the ON state. As a result, the V_th distribution of the floating gate transistor can be wider and the programming can be faster because the number of program/verify cycles can be reduced. Furthermore, the SWATT cell results in a very small cell size of 0.57 μm² for a 0.35 μm rule. Thus, the SWATT cell combines a small cell size with a multi-level scheme to realize a very low bit cost. This paper describes the process technology and the device performance of the SWATT cell, which can be used to realize NAND EEPROM's of 512 Mbit and beyond     

Finite-difference time-domain analysis and experimental examinationof the performance of a coupled-cavity MQW laser/active waveguide at1.54 μm

The performance characteristics of a coupled cavity InGaAsP-InP MQW laser/active waveguide made by one-step epitaxy and well-controlled reactive ion etching (RIE) have been theoretically analyzed and experimentally determined. A theoretical model based on a finite-difference time-domain (FDTD) technique was used to simulate the propagation of an optical wave launched in the coupled system and determine the reflectivity of the facets created by RIE. The calculated effective reflectivity of the coupling region consisting of two facets and an air gap is between 0.45 and 0.55, which is in good agreement with the experimentally measured value of 0.5. The reflectivity of a single etched mirror derived from this value is estimated to be 0.3. A 120-μm-long monolithically integrated active waveguide when biased as a modulator and excited by the laser shows a maximum extinction ratio of 8 dB and a modulation bandwidth ⩾14 GHz at a dc bias of -0.5 V with a bias swing of 2 V     

Microprocessor-based random PWM schemes for DC-AC power conversion

Two classes of microprocessor-based random PWM (RPWM) real-time schemes for DC-AC power conversion are compared and evaluated. Performance of the RPWM schemes based on mathematical and logical approaches is examined. The proposed schemes exhibit excellent harmonic content with all low and high-order harmonics suppressed, and are suitable for both MOSFET and IGBT inverters     

Subharmonic synchronous and hybrid mode-locking of a monolithic DBR laser operating at millimeter-wave frequencies

A detailed comparison of subharmonic synchronous and subharmonic hybrid mode-locking of a monolithic distributed Bragg reflector (DBR) laser operating at 33 GHz is presented. Optical injection at the 20th subharmonic frequency (1.65 GHz) has produced a locking range of 10 MHz with negligible amplitude modulation. In comparison, electrical injection at the 4th subharmonic frequency (5.83 GHz) has shown higher levels of amplitude modulation and a narrower locking range (4 MHz). While subharmonic hybrid mode-locking remains a simple and cost effective solution for the generation of low timing jitter high-repetition rate optical pulse trains, subharmonic synchronous mode-locking shows superior performance with regard to reduced amplitude modulation and larger locking range.     

Automatic extraction and measurement of leukocyte motion inmicrovessels using spatiotemporal image analysis

This paper describes a computer vision system for the automatic extraction and velocity measurement of moving leukocytes that adhere to microvessel walls from a sequence of images. The motion of these leukocytes can be visualized as motion along the wall contours. The authors use the constraint that the leukocytes move along the vessel wall contours to generate a spatiotemporal image, and the leukocyte motion is then extracted using the methods of spatiotemporal image analysis. The generated spatiotemporal image is processed by a special-purpose orientation-selective filter and a subsequent grouping process newly developed for this application. The orientation-selective filter is designed by considering the particular properties of the spatiotemporal image in this application in order to enhance only the traces of leukocytes. In the subsequent grouping process, leukocyte trace segments are selected and grouped among all the segments obtained by simple thresholding and skeletonizing operations. The authors show experimentally that the proposed method can stably extract leukocyte motion     

A 2-V, 1-10 GHz BiCMOS transceiver chip for multimode wirelesscommunications networks

This paper concerns the design consideration, fabrication process, and performance results for an ultra-broadband, low-voltage, low-power, BiCMOS-based transceiver chip for cellular-satellite-LAN wireless communication networks. The transceiver chip incorporates an RF amplifier, a Gilbert down-mixer, and an IF amplifier in the receive path, and an IF amplifier, a Gilbert up-mixer, and an RF amplifier in the transmit path. For an RF frequency in the 1-10 GHz band and an IF frequency in the 100-1000 MHz band, the developed transceiver chip consumes less than 60 mW at 2 V, to yield a downconversion gain of 40 dB at 1 GHz and 10 dB at 10 GHz and an upconversion gain of 42 dB at 1 GHz and 11 dB at 10 GHz. To avoid possible start-up problems caused during “stand-by” to “enable” mode transition, a simple switching technique is employed for enabling either the receive or the transmit path, by changing the value of a reference voltage applied to both the down- and the up-mixers. While the developed transceiver chip exhibits the best performance for a dc supply voltage of 2 V, it shows a graceful degradation for a ±0.15 V voltage deviation. The transceiver's chip size is 1.04 mm×1.04 mm     

A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byteeffective program speed

Emerging application areas of mass storage flash memories require low cost, high density flash memories with enhanced device performance. This paper describes a 64 Mb NAND flash memory having improved read and program performances. A 40 MB/s read throughput is achieved by improving the page sensing time and employing the full-chip burst read capability. A 2-μs random access time is obtained by using a precharged capacitive decoupling sensing scheme with a staggered row decoder scheme. The full-chip burst read capability is realized by introducing a new array architecture. A narrow incremental step pulse programming scheme achieves a 5 MB/s program throughput corresponding to 180 ns/Byte effective program speed. The chip has been fabricated using a 0.4-μm single-metal CMOS process resulting in a die size of 120 mm² and an effective cell size of 1.1 μm²     

Equiripple FIR filter design by the FFT algorithm

The fast Fourier transform (FFT) algorithm has been used in a variety of applications in signal and image processing. In this article, a simple procedure for designing finite-extent impulse response (FIR) discrete-time filters using the FFT algorithm is described. The zero-phase (or linear phase) FIR filter design problem is formulated to alternately satisfy the frequency domain constraints on the magnitude response bounds and time domain constraints on the impulse response support. The design scheme is iterative in which each iteration requires two FFT computations. The resultant filter is an equiripple approximation to the desired frequency response. The main advantage of the FFT-based design method is its implementational simplicity and versatility. Furthermore, the way the algorithm works is intuitive and any additional constraint can be incorporated in the iterations, as long as the convexity property of the overall operations is preserved. In one-dimensional cases, the most widely used equiripple FIR filter design algorithm is the Parks-McClellan algorithm (1972). This algorithm is based on linear programming, and it is computationally efficient. However, it cannot be generalized to higher dimensions. Extension of our design method to higher dimensions is straightforward. In this case two multidimensional FFT computations are needed in each iteration     

SIR and SNR improvement in wideband beamspace array processing

Owing to limitations of frequency resources, advanced sensor array processing techniques are needed in a growing wireless wideband communications market. A beamspace wideband processing technique is proposed and is shown to reduce both signal to interference and SNR ratios. Performances for different array processing algorithms, flexibility and complexity cost are thus improved