Gate-induced drain-leakage in buried-channel PMOS-a limiting factorin development of low-cost, high-performance 3.3-V, 0.25-μmtechnology

This paper presents a low cost 0.25-μm technology with low standby power for 3.3 V applications. It is shown that as a single gate oxide n-type polysilicon gate technology is scaled, gate-induced drain-leakage (GIDL) in buried-channel PMOS becomes a serious limiting factor in achieving low standby power. The impact of technology choices such as spacer material, spacer width and poly reoxidation conditions on PMOS GIDL is discussed. A technology that successfully limits PMOS leakage is presented     

Efficient greedy feature selection for unsupervised learning

Reducing the dimensionality of the data has been a challenging task in data mining and machine learning applications. In these applications, the existence of irrelevant and redundant features negatively affects the efficiency and effectiveness of different learning algorithms. Feature selection is one of the dimension reduction techniques, which has been used to allow a better understanding of data and improve the performance of other learning tasks. Although the selection of relevant features has been extensively studied in supervised learning, feature selection in the absence of class labels is still a challenging task. This paper proposes a novel method for unsupervised feature selection, which efficiently selects features in a greedy manner. The paper first defines an effective criterion for unsupervised feature selection that measures the reconstruction error of the data matrix based on the selected subset of features. The paper then presents a novel algorithm for greedily minimizing the reconstruction error based on the features selected so far. The greedy algorithm is based on an efficient recursive formula for calculating the reconstruction error. Experiments on real data sets demonstrate the effectiveness of the proposed algorithm in comparison with the state-of-the-art methods for unsupervised feature selection.     

Guided Locally Linear Embedding

Nonlinear dimensionality reduction is the problem of retrieving a low-dimensional representation of a manifold that is embedded in a high-dimensional observation space. Locally Linear Embedding (LLE), a prominent dimensionality reduction technique is an unsupervised algorithm; as such, it is not possible to guide it toward modes of variability that may be of particular interest. This paper proposes a supervised variation of LLE. Similar to LLE, it retrieves a low-dimensional global coordinate system that faithfully represents the embedded manifold. Unlike LLE, however, it produces an embedding in which predefined modes of variation are preserved. This can improve several supervised learning tasks including pattern recognition, regression, and data visualization.     

Developing a practical framework for ERP readiness assessment using fuzzy analytic network process

Previous studies report unusually high failure in enterprise resource planning (ERP) projects. Thus, it is necessary to perform an assessment at the initial stage of an ERP implementation program to identify weaknesses or problems which may lead to project failure. No definite practical solution could be found for these kinds of problems in the literature. In this paper, a new look at the determinants of a firm’s readiness to implement an ERP project is presented and using fuzzy analytic network process a practical framework is developed. The firm’s current conditions regarding ERP project can be determined and necessary changes prior to implementation of ERP system can be specified. The readiness for ERP implementation is decomposed into project management, organizational, and change management areas and the assessment factors are identified after comprehensive study of critical success factors on ERP implementation. The proposed framework is applied to a real case and the advantages are illustrated.     

Scheduling to minimize gaps and power consumption

This paper considers scheduling tasks while minimizing the power consumption of one or more processors, each of which can go to sleep at a fixed cost  $\alpha $ . There are two natural versions of this problem, both considered extensively in recent work: minimize the total power consumption (including computation time), or minimize the number of “gaps” in execution. For both versions in a multiprocessor system, we develop a polynomial-time algorithm based on sophisticated dynamic programming. In a generalization of the power-saving problem, where each task can execute in any of a specified set of time intervals, we develop a $(1+{2 \over 3} \alpha )$ -approximation, and show that dependence on $\alpha $ is necessary. In contrast, the analogous multi-interval gap scheduling problem is set-cover hard (and thus not $o(\lg n)$ -approximable), even in the special cases of just two intervals per job or just three unit intervals per job. We also prove several other hardness-of-approximation results. Finally, we give an $O(\sqrt{n})$ -approximation for maximizing throughput given a hard upper bound on the number of gaps.     

Surface morphology and optoelectronic studies of sol–gel derived nanostructured CdO thin films: heat treatment effect

Morphological dependence of the optoelectronic properties of sol–gel derived CdO thin films annealed at different temperatures in air has been studied. After preparing, the films were investigated by studying their structural, morphological, d.c. electrical and optical properties. X-ray diffraction results suggest that the samples are polycrystalline and the crystallinity of them enhanced with annealing temperature. The average grain size is in the range of 12–34?nm. The root mean square roughness of the films was increased from 3.09 to 6.43?nm with annealing temperature. It was observed that the electro-optical characteristics of the films were strongly affected by surface roughness. As morphology and structure changed due to heat treatment, the carrier concentration was varied from 1.13?×?10¹⁹ to 3.10?×?10^19?cm^?3 with annealing temperature and the mobility increased from less than 7 to 44.8?cm² V^?1 s^?1. It was found that the transmittance and the band gap decreased as annealing temperature increased. The optical constants of the film were studied and the dispersion of the refractive index was discussed in terms of the Wemple–DiDomenico single oscillator model. The real and imaginary parts of the dielectric constant of the films were also determined. The volume energy loss increases more than the surface energy loss at their particular peaks.     

An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding

Redundant and hybrid-redundant number representations are used extensively to speed up arithmetic operations within general-purpose and special-purpose digital systems, with the latter (containing both redundant and nonredundant digits) offering cost advantages over fully redundant systems. We use weighted bit-set (WBS) encoding as a paradigm for uniform treatment of five previously studied variants of hybrid-redundant systems. We then extend the class of hybrid-redundant numbers to coincide with the entire set of canonical WBS numbers by allowing an arbitrary nonredundant position, heretofore restricted to ordinary bits (posibits), to hold a negatively weighted bit (negabit). This flexibility leads to interesting and useful symmetric variants of hybrid-redundant representations. We provide a high-level circuit design, based solely on binary full-adders, for a constant-time universal hybrid-redundant adder capable of producing a canonical WBS-encoded sum of two canonical WBS (or extended hybrid) numbers. This is made possible by the use of conventional binary full-adders for reducing any collection of three posibits and negabits, where negabits use an inverted encoding. We compare our adder to previous designs, showing advantages in speed, cost, and regularity. Furthermore we explore representationally closed addition schemes, holding the benefit of greater regularity and reusability, and provide high-level representationally closed designs for all the previously studied variants of hybrid redundancy and for the new symmetric variants introduced here. Finally, we present a new functionality for a conventional (4; 2) compressor in combining any collection of five equally weighted negabits and posibits, and show its utility in the design of multipliers for extended hybrid-redundant numbers. Ghassem Jaberipur received BS in electrical engineering and PhD in computer engineering from Sharif University of Technology in 1974 and 2004, respectively, MS in engineering (majoring in computer hardware) from University of California, Los Angeles, in 1976, and MS in computer science from University of Wisconsin, Madison, in 1979. Since 1979, he has been with the Department of Electrical and Computer Engineering, Shahid Beheshti University, in Tehran, Iran, teaching courses in compiler construction, automata theory, design and implementation of programming languages, and computer arithmetic. Behrooz Parhami (PhD, University of California, Los Angeles, 1973) is Professor of Electrical and Computer Engineering at University of California, Santa Barbara. He has research interests in computer arithmetic, parallel processing, and dependable computing. In his previous position with Sharif University of Technology in Tehran, Iran (1974--88), he was also involved in educational planning, curriculum development, standardization efforts, technology transfer, and various editorial responsibilities, including a five-year term as Editor of Computer Report, a Persian-language computing periodical. His technical publications include over 200 papers in peer-reviewed journals and international conferences, a Persian-language textbook, and an English/Persian glossary of computing terms. Among his publications are three textbooks on parallel processing (Plenum, 1999), computer arithmetic (Oxford, 2000), and computer architecture (Oxford, 2005). Dr. Parhami is a Fellow of both the IEEE and the British Computer Society, a member of the Association for Computing Machinery, and a Distinguished Member of the Informatics Society of Iran for which he served as a founding member and President during 1979-84. He also served as Chairman of IEEE Iran Section (1977-86) and received the IEEE Centennial Medal in 1984. Mohammad Ghodsi Mohammad Ghodsi received BS in electrical engineering from Sharif University of Technology (SUT, Tehran, Iran) in 1975, MS in electrical engineering and computer science from University of California at Berkeley in 1978, and PhD in computer science from the Pennsylvania State University in 1989. He has been affiliated with SUT as a faculty member since 1979. Presently, he is a Professor in SUT's Computer Engineering Department. His research interests include design of efficient algorithms, parallel and systolic algorithms, and computational geometry.     

Physical characteristics modification of a SiGe-HBT semiconductor device for performance improvement in a terahertz detecting system

In order to improve the performance of a pre-designed direct conversion terahertz detector which is implemented in a 0.25 μ m-SiGe-BiCMOS process, we propose some slight modifications in the bipolar section of the SiGe device physical design. Comparison of our new proposed device and the previously reported device is done by SILVACO TCAD software simulation and we have used previous experimentally reported data to confirm our software simulations. Our proposed modifications in device structural design show a present device responsivity improvement of about 10% from 1 to 1.1 A/W while the bandwidth improvement is about 218 GHz. The minimum noise equivalent power at detector output is increased by about 14.3% and finally power consumption per pixel at the maximum responsivity is decreased by about 5%.     

Automatic dimensionality selection from the scree plot via the use of profile likelihood

Most dimension reduction techniques produce ordered coordinates so that only the first few coordinates need be considered in subsequent analyses. The choice of how many coordinates to use is often made with a visual heuristic, i.e., by making a scree plot and looking for a “big gap” or an “elbow.” In this article, we present a simple and automatic procedure to accomplish this goal by maximizing a simple profile likelihood function. We give a wide variety of both simulated and real examples.