静态图像中的人体行为分类研究

静态图像中人体行为分类的一般方法是先手动标定出行为对象,再单独对行为对象进行特征提取和分析,不仅费时费力还丢失了场景信息。针对此问题提出了结合场景特征与行为对象特征的图像表示方法,充分利用图像的所有信息。此外为了减小量化误差,在特征编码阶段,采用局部约束线性编码(Locality-constrained Linear Coding,LLC)算法,并将其应用在空间金字塔模型的向量量化中。该算法与传统的矢量量化算法和稀疏编码算法相比,能够降低量化误差。最后在Stanford 40 Action数据集上对文中方法进行实验和验证,结果表明,结合场景特征与行为对象特征并使用LLC编码算法能够获得更好的分类效果。     

Mixed analog-digital crossbar-based hardware implementation of sign–sign LMS adaptive filter

Recently announcement of a physical realization of a fundamental circuit element called memristor by researchers at Hewlett Packard (HP) has attracted so much interest worldwide. Combination of this newly found element with crossbar interconnect technology, opened a new field in designing configurable or programmable electronic systems which can have applications in signal processing and artificial intelligence. In this paper, based on the simple memristor crossbar structure, we will propose a new mixed analog-digital circuit as a hardware implementation of the sign–sign least mean square (LMS) adaptive filter algorithm. In this proposed hardware, any multiplication and addition is performed with infinite precision and there is no necessity for the quantization of the input signal. Since the coefficients of the filter are stored in the switches of the crossbar, they can remain unchanged theoretically for an infinite period of time.     

An improved low offset latch comparator for high-speed ADCs

This paper presents a new high-speed and low offset latch comparator. The proposed offset compensation technique for latch comparator enables the preamplifier design relaxation for high-speed and high-resolution analog-to-digital converters. Employing the negative resistance of regeneration latch to enhance the comparator gain in input tracking phase is the key idea to reduce the latch input referred offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that equivalent input referred offset voltage is 200 μV at 1 sigma while it was 26 mV at 1 sigma before offset cancellation. The comparator dissipates 600 μW from a 1.8 V supply while operating in 500 MHz clock frequency.     

A 400-mA current-mode buck converter with a self-trimming current sensing scheme

A current-programmed mode (CPM) controller is designed for improved DC–DC converter control. The key building block of the CPM controller is an accurate current-sensing circuit. This paper proposes a lossless current-sensing technique to measure the inductor current by measuring the current through the power transistor. A self-trimming circuit is used to compensate for any inaccuracies caused by voltage and temperature variations. The measurement results validate the operation of the fabricated chip.     

High efficiency,high switching speed,AlGaAs/GaAs P-HEMT DC–DC converter for integrated power amplifier modules

This paper presents a high efficiency, high switching frequency DC–DC buck converter in AlGaAs/GaAs technology, targeting integrated power amplifier modules for wireless communications. The switch mode, inductor load DC–DC converter adopts an interleaved structure with negatively coupled inductors. Analysis of the effect of negative coupling on the steady state and transient response of the converter is given. The coupling factor is selected to achieve a maximum power efficiency under a given duty cycle with a minimum penalty on the current ripple performance. The DC–DC converter is implemented in 0.5 μm GaAs p-HEMT process and occupies 2 × 2.1 mm² without the output network. An 8.7 nH filter inductor is implemented in 65 μm thick top copper metal layer, and flip chip bonded to the DC–DC converter board. The integrated inductor achieves a quality factor of 26 at 150 MHz. The proposed converter converts 4.5 V input to 3.3 V output for 1 A load current under 150 MHz switching frequency with a measured power efficiency of 84%, which is one of the highest efficiencies reported to date for similar current/voltage ratings.     

On-chip offset generator for accurate integral non-linearity testing of A/D converters and D/A-A/D converter pairs

It has recently shown how a constant dc offset between two low-quality test signals can be used to test the integral nonlinearity (INL) of A/D converters (ADCs) without an accurate test stimulus, and how the same method can be used to test the INL of D/A converters (DACs) as well. We propose here an on-chip offset generator for producing the constant offset and analyse its limitations. Experimental tests on the 122 × 22 μm² offset generator fabricated in 130 nm CMOS process show that it can be used to test the INL of 12-b DACs and ADCs. The generator is rail-to-rail capable so that almost the whole input/output range of converters can be tested. Moreover, if the proposed offset generator is used in a ratiometric test setup as proposed here as well, the influence of a reference voltage drift on measurement accuracy is cancelled out. Because of its small size, simple design, rail-to-rail capability and immunity to reference voltage changes, the proposed offset generator is well suited for built-in self-test usage.     

Optimal cluster-based routing scheme using node mobility in ad hoc networks

Ad hoc networks have a scalability problem. When the nodes of an ad hoc network increase in number or mobility, the amount of control traffic for routing increases and could cause traffic congestion. Cluster-based routing schemes have been proposed as a solution to this problem. Typical cluster-based ad hoc networks use a proactive routing scheme for intra-cluster routes and a reactive routing scheme for inter-cluster routes. In this study, we propose a new cluster-based routing scheme for ad hoc networks which makes use of the mobility of nodes. Nodes are divided into two groups on the basis of their mobility. For a route search within a cluster, a proactive routing scheme is used for low-mobility nodes and a flooding-based reactive routing scheme is used for high-mobility nodes. The required control traffic of the proposed scheme is analyzed and optimal parameters of the proposed scheme are derived from the analysis. The numerical results show that the proposed scheme produces far less control traffic than a typical cluster-based routing scheme.     

Capacity-achieving probability measure for a reduced number of signaling points

Putting bounding constraints on the input of a channel leads in many cases to a discrete capacity-achieving distribution with a finite support. Given a finite number of signaling points, we determine reduced subsets and the corresponding optimal probability measures to simplify the receiver design. The objective for the subset selection is to keep the channel quality high by maximizing mutual information and cutoff rate. Two approaches are introduced to obtain a capacity-achieving probability measure for the reduced subset. The first one is based on a preceded signaling point selection while the second one chooses the signaling points and corresponding probabilities simultaneously. Numerical results for both approaches show that using only a small number of signaling points achieves a very high mutual information compared to channels utilizing the full set of signaling points.     

On Adaptive Density Deployment to Mitigate the Sink-Hole Problem in Mobile Sensor Networks

The use of mobile sensors is of great relevance to monitor critical areas where sensors cannot be deployed manually. The presence of data collector sinks causes increased energy depletion in their proximity, due to the higher relay load under multi-hop communication schemes (sink-hole phenomenon). We propose a new approach towards the solution of this problem by means of an autonomous deployment algorithm that guarantees the adaptation of the sensor density to the sink proximity and enables their selective activation. The proposed algorithm also permits a fault tolerant and self-healing deployment, and allows the realization of an integrated solution for deployment, dynamic relocation and selective sensor activation. We formally prove the termination of our algorithm. Performance comparisons between our proposal and previous approaches show how the former can efficiently reach a deployment at the desired variable density with moderate energy consumption under a wide range of operative settings.     

A latency-aware scheduling algorithm for all-optical packet switching networks with FDL buffers

Optical buffers implemented by fiber delay lines (FDLs) have a volatile nature due to signal loss and noise accumulation. Packets suffer from excessive recirculation through FDLs, and they may be dropped eventually in their routing paths. Because of this, packet scheduling becomes more difficult in FDL buffers than in RAM buffers, and requires additional design considerations for reducing packet loss. We propose a latency-aware scheduling scheme and an analytical model for all-optical packet switching networks with FDL buffers. The latency-aware scheduling scheme is intended to minimize the packet loss rate of the networks by ranking packets in the optimal balance between latency and residual distance. The analytical model is based on non-homogeneous Markovian analysis to study the effect of the proposed scheduling scheme on packet loss rate and average delay. Furthermore, our numerical results show how various network parameters affect the optimal balance. We demonstrate quantitatively how to achieve the proper balance between latency and residual distance so that the network performance can be improved significantly. For instance, we find that under a given latency limit and light traffic load our scheduling scheme achieves a packet loss rate 71% lower than a scheduling scheme that ranks packets simply based on latency.